If reo_dst_ctrl register writing failed, this is a fatal error for
IPA pipe going to down case as RX frames will still be routed to
IPA rings then hit NOC error. retry register writing to see any
chance to write successfully, if fail always, trigger SSR or panic.
Change-Id: I3c03faa28e6cc93f396944579a360d5405c8138e
CRs-Fixed: 2774789
The logging macros implicitly takes care of embedding function name
in the log, hence there is no need to include __func__ again.
Getting rid of redundant __func__ reduces driver memory footprint.
Change-Id: I6b5beea990e78486e1e5aab5a8df5fc2f1e5ab51
CRs-Fixed: 2774457
MSDU count is not reliable in all cases.Hence it is better
to check whether next_link_desc is valid or not and then
free the MSDUs in the next descriptor and subsequently
release both the current and next link descriptor back to HW.
Change-Id: Ie5ea3be547f9aed6673293221f6b47661cd92cce
STATUS_BUFFER_DONE tlv written in first word for a status
buffer indicates that DMA is done for that status ring entry.
In existing implementation, for a status ring entry if
STATUS_BUFFER_DONE tlv is not written by HW, we poll on to status ring
entry until DMA is done by HW.
During lmac reset it may happnen that HW will not write STATUS_BUFFER_DONE
tlv in status buffer, in that case we end up polling infinitely leading
to backpressure on monitor status ring.
As per MAC team's suggestion, when HP + 1 entry is peeked and if DMA
is not done and if HP + 2 entry's DMA done is set,
replenish HP + 1 entry and start processing in next interrupt.
If HP + 2 entry's DMA done is not set,
poll onto HP + 1 entry DMA done to be set.
CRs-Fixed: 2740988
Change-Id: Ieef667f0bb4a47e74fc320c93243c637409f47f0
HAL changes to fetch cfr information from
PHYRX_PPDU_END_TLV & RXPCU_PPDU_END TLV
Change-Id: I5817fdc5d17ebea3f2376b7bef9e58981198d1ec
CRs-Fixed: 2752943
Memory optimization of monitor status ring by allocating buffers during
replenish using alloc_skb (linux API).
It creates buffer of required size rather than 4k size(dev_alloc_skb)
Change-Id: I3ae5e403de28c4570f8ac3b50d3ca878a9e4b2f9
CRs-Fixed: 2733931
When matching ppdu_id is detected during HAL processing, then print the
error message instead of going for assert.
Change-Id: I8f58359a66fbeaf2ebc98477f65bab446c0a784b
CRs-Fixed: 2747953
In monitor mode, radiotap header contains VHT/HE information in management
and control frames after association of STA to AP.For this,reset of
ppdu_info is required before processing of ppdu in order to avoid reuse
of ppdu_info.
Change-Id: Ia36ec2664f79d645ff76db016f986dfb92ec8bbd
CRs-Fixed: 2734804
In QC9000, the channel capture status gets update in reserved_8
field's lower 2 bits only. Remaining bits are used for debug.
CRs-Fixed: 2740908
Change-Id: I97321addb18f8e5944f5f58d670dfa9858dca4ec
Before accessing any register on chip 6750, check if target is
ready or not.
Do not allow register access if target is not ready.
Change-Id: I41a604d04e861c97bdd676998222ccecbf12fd5a
CRs-Fixed: 2688920
On returning the msdu link descriptor to HW via WBM
release ring, the rx exception ring contents are not
zeroed. This could result in host reading stale ring
descriptor content in the scenario when HP is updated
even before the latest values are reflected in the ring
descriptor.
Fix is to set invalid bit in cookie for exception ring
descriptor and add cookie sanity check.
Change-Id: I01a294c92b260ebe8e584ef20e9550b1febec913
CRs-Fixed: 2730759
When an AP operates on a 6G channel. The channel frequency in the
radiotap header, in the beacon frame, shows an incorrect 6G frequency.
This is because, the function hal_rx_radiotap_num_to_freq is not updated
to handle the 6G channelization spec update ( IEEE 802.11 11AX Draft 6.1).
To fix this issue, update the function hal_rx_radiotap_num_to_freq to
handle the 6G channelization spec update (increase the 6G frequencies by
an offset of 10MHz).
Change-Id: I342dcb46b2627b3a2c3f12524077e63d811a5feb
CRs-Fixed: 2733367
For MCC, hash key related member in struct hal_rx_fst is not used,
it requires big chunk memory > 40K bytes that sometimes may fail to
allocate from system, wlan start up failed.
Remove hash key related member in hal_rx_fst by macro
WLAN_SUPPORT_RX_FISA for MCC.
Change-Id: I4214e18155c3ebc3dcc800c8c74f7eed16d580b4
CRs-Fixed: 2732990
Make sure to drop the raw Rx frames as both driver and stack
are not expected to handle them.
Add counter for invalid fisa flow_idx packet received.
Change-Id: I5107c554b8ce6a9a7973f2aeca44bb0f360dc2df
CRs-Fixed: 2733981
Currently all the rx ring descriptor contents are left
intact even after these entries are processed. This can,
at times, lead to stale entries being processed, if the
head pointer of any ring is updated before the updated
contents of the ring descriptor gets reflected in the memory.
This can lead to scenarios where the host driver reads a
stale value of sw_cookie, and free/unmap a currently in-use
buffer, thereby leading to the hardware accessing unmapped
memory region.
The sw_cookie is the integral part of al the rx ring
processing. Hence we always mark the sw_cookie as invalid
after dequeuing an entry from the REO2SW ring. Every time
we check for the validity of the sw_cookie before we try to
process an entry from REO2SW ring. if the invalid bit in the
sw_cookie is set, we just skip this entry and move on to the
next entry in the ring.
Change-Id: I0e78fa662b8ba33e64687a4dee4d1a5875ddb4bf
CRs-Fixed: 2730718
Remove uncessary msdu count check against msdu count in
mpdu desc info while processing REO Rx err pkts.
As per h/w team msdu count can be obtained from msdu link
desc instead of mpdu desc info.
SOC level Rx err stat rx.err.msdu_count_mismatch is
incremented to log this condition.
Change-Id: I4f7d2df7335778f2f2d28e542da17fc7f6970009
CRs-Fixed: 2729693
Rxdma decrypt errors are observed when the association
is in progress as AP sends encrypted data packets to
DUT-STA. As part of the rxdma error handling, excessive
prints are logged to console resulting in an assert.
Fix is to rate limit rxdma decrypt error related log
Change-Id: I2ef28c635d77e3acafd067b921cdb13c277756c7
CRs-Fixed: 2725335
Adding support for enabling ini config to remap reo destination rings
for HK v1, HK v2, maple and pine platforms.
Change-Id: Id9d304521f32497e3acd845ddd2973b96b641516
After enabling FISA, getting compilation issue in WHUNT due to
-Werror=maybe-uninitialized.
Fix this issue by initializing the uninitialized variables.
Change-Id: I4bdb76ba445630fb09df440f587291f0c3e382ec
CRs-Fixed: 2717632
Configure low threshold for monitor ring only when monitor
vap is created. This is needed to avoid spurious low threshold
interrupts on monitor ring since the low threshold condition always
evaluates to true.
Change-Id: I452c0ada84e0a4f18e410c865d8a6a7f50329aef
PCIe window select config reg update goes on different NoC and
actual PCIe device register access goes on the different NoC.
If there is delay in window select reg config, it can result in
access some other PCIe IO memory access and will result in actual
register write lost issue. Make sure to flush the window select
reg write before actual device reg access.
Change-Id: I1fe17aad7ae8fd5dea7a618273d9cd813b236a85
CRs-Fixed: 2687676
Due to changes in datapath init/deinit path, mon_lock spinlock was not
getting created. Create mon_lock spinlock during
dp_rx_pdev_mon_cmn_desc_pool_init.
Add null check to validate rx_tlv_header before calling
hal_rx_mpdu_start_tlv_tag_valid.
Change-Id: I41c781de29f2c8c05ec1bfa90f9c8f742f2539bf
CRs-Fixed: 2693687
On Lahaina platform it is seen that WBM IDLE ring init is failing,
Write to WBM_IDLE link ring LSB write is failing.
Add temporary WAR to do back to back write of WBM IDLE link ring
LSB address config register.
Change-Id: If0c20da06bafa3037845e9806934f9e4dfbd1c1c
CRs-Fixed: 2690495
In ipq5018 CE registers(0x08400000) kept outside WCSS(0x0C000000) block.
As both regions are more than 60MB apart, not feasible to allocate
single resource which include both.
So, using a separate I/O region to access CE registers.
Change-Id: I67bb6d5ac82a1c0ed1d3e13f7776f9d69ee19956
MPDU start TLV structure is different across pine and hk/cyp. The
access to individual members of this structure is already taken care
in HAL APIs.
Tha addition of offset is redundant and wrongly defined offset values
led to wrong interpretation of mpdu start tlv fields like RSSI in
QCN9000.
Change-Id: I3c0daa1c9117eecd1566a1d52d794e92dc292fa4
CRs-Fixed: 2682570
make sure both PCIe and device are force woken for the register
writes for hsp, or write may fail.
Earlier WAR is not required as we have root caused it.
Change-Id: I350b810a6cef8eec46428e57f5b779f888552c1b
CRs-Fixed: 2677342
Currently as part of runtime PM, only the active
tasklets are being drained. For chips eg. QCA6390,
QCA6490 etc, there are grp_tasklets and delayed reg
write work which has to be drained before entering
runtime PM.
Add the logic to drain all the possible tasks
before entering runtime PM.
Change-Id: Ieb486f00fffd7346dcdc1faea6fed5850ef6daf7
CRs-Fixed: 2676000
rts full destination address is needed to be able to do check on mac
to be able to recreate cts frame correspondingly.
Change-Id: I3ec7e765bb4a0645a1495b4ca42d81fd3134cc5d
Lot of checks in Tx completion path are for special handlings
such as when ol stats are enabled some protective debug checks etc..
Add a logic to fast free of buffer at transmit completion.
If extended stats not enabled(Typically needed for enterprise cases)
do the buffer free faster. This is controlled through a flag.
Change-Id: I04873b5e3643d8e93e5b248fcaf23504dcb7624f
Currently, mcopy mode delivers first msdu(fcs_passed 128 bytes) per-ppdu
to upper layer, add support for Extended mcopy mode to deliver first
msdu(128 bytes) per-MPDU(fcs_passed).
Change-Id: Ib345fc14a8d468788b9de78516d27e8dff24caa4
CRs-Fixed: 2644175
Added below chip specific changes for ipq5018
1. Read ppdu_id from reo_entrance ring
2. API to extract msdu end pkt tlv information at once
and store in local structure
Change-Id: Ic23bbd03db0e4ac56d40618378dc4d428f88d083
Do batched invalidate of tx completion descriptor to avoid
unnecessary D-cache miss for 32 byte size descriptor.
Change-Id: Ia580fe78dcef5b36f117aaad171a2df6d0e34966
Add prefetch_timer configuration for CE rings.
Set prefetch_timer=1 configuration for qca6490 destination CEs,
prefetch_timer=0 configuration for other targets CEs.
Basically setting to 1us asking CE hw to update ring tail pointer to
update within 1us. FW side CE SW sets all rings to 1us already.
Idea behind this change is, we have seen pre-silicon issue where SRC
ring TP read by SW was not seen updated value when prefetch was set
to 8us. Changing prefetch timer value to 1us helps to resolve
pre-silicon issue.
So host side rings need to update the prefetch timer to 1us.
Change-Id: I0830c73517c29cf39e6b2974bf3faa44e5673741
CRs-Fixed: 2669762
Size of the TLVs have changed across generation of chipsets
Offset values need to be configured into DMA register for preheader DMA
Added APIs to get offsets of each TLV based on chip type
Change-Id: Ic011332cbf3a1017f324f246e47c9e2c91441c70
The delayed register write enqueue fills a queue element
with the required data which can be dequeued in a workqueue
running on a different CPU. Since these operations are not
lock protected, there can be stale value access when memory
write has not been flushed to the actual address.
Using write memory barrier before setting the valid flag for
a queue element will make sure that the dequeuing worker
thread will always see the updated values if the element valid
flag is set and thereby avoid any race condition.
Change-Id: I81b0735f0fb39599095ad309157020c691e25a0b
CRs-Fixed: 2665576
