Currently aggresive idle-pc entry is only enabled in
case of doze-suspend mode. Extend the support to doze
mode as well.
Change-Id: I8e9e0e116bb65a1aec0180bf9bc10bed99d4a137
Signed-off-by: Govinda Rao K S <quic_gkarikur@quicinc.com>
Currently, driver enforces the allocated WB output buffer to be 256 bits
aligned in memory in order to optimize DDR access and meet maximum system
bandwidth requirements.
Since there are no functional failures with using a 256 bits unaligned
buffer, this change removes this unnecessary check.
Change-Id: I23476e8a28e970f2e1853bbcc0c1d1042d9fdfe2
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Enable trusted vm flag for kalama target
Change-Id: I2f2c0a838914d5fccf6642690c082c592e04e38d
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
SID registers and offsets are changed in display
MDSS 9.0.0. Changes are made to program these new registers.
Also, added new revision check for backward
compatibility.
Change-Id: I4e1ea374f38c95a4d1019c2596418bb6bb7c5347
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
This change adds the programming of the master interface
register for single interface configurations.
Setting this register is required by hw-fencing feature
to distinguish primary interfaces vs wb.
Change-Id: I84936ebd6a9f2d67cf98c19a51ce3a132c648a2d
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change avoids null pointer dereference in different APIs.
Change-Id: I01eba9d64fa4ba2fd81f7f39f586867e22d66771
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
MDSS 9.0.0 added support for logging MDP_VSYNC timestamp. Use it for
video-mode panels and rely on PANEL_VSYNC timestamp for cmd-mode panels
as it relies on external panel TE.
Change-Id: I09b25d893075bee7cb2da98d4c4b4e54eb09bd6e
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
With MDSS 9.0.0, s/w relies on the ctl-done-irq which signifies the
frame done for the ctl path. Avoid unnecessary waits during
tx-done/commit-done on the individual physical encoders when ctl-done
feature is enabled.
Change-Id: Ie5e8b08c47a4778dfa03a87dbbae8daf6a738e6a
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Fix the Watchdog timer load value calculation with jitter feature.
Change the long term jitter value check to have jitter < 10.
Change-Id: If834e16d3b8fad5009642e479f529fa5b7cf2d17
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add check to avoid more than 1 CWB active per commit as
hardware doesn't support multiple CWB even if they are
on different OP.
Change-Id: I13416cc2af881de0d8bdd6544a4fdc180fb7a050
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Avoid read/update for WD_TIMER_0_CTL2 register as the default value changed
from MDSS 9.x.x to disable clock granularity and this leads to issues with
VSYNC generation. Instead program the necessary configs directly.
Change-Id: Id545ad772480f94cf432bff8e8bfeb2b679f8aa9
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Ensure SDE_ERROR error log print function name and line number.
Add a macro DISP_DEV_ERR as a wrapper of dev_err to ensure origin dev_err
will print function name and line number.
This would help with analysis of errors reported with automated testing.
Expected display error log format:
[FUNCTION_NAME:line] ERROR_MESSAGE
Change-Id: I354f45b492059d5ba2bb110d56443fd338add7ad
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
If display cont-splash is enabled, then sde irq will be enabled
after registration, but sde power event assumes irq to be disabled
by default and will still try to enable irq with first power event
call, then could cause unbalanced irq enable warning on boot up.
Change-Id: Ic5482dd06501721664994f77cd5764140afb7a62
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
The sde power event function needs to get actual sde kms irq
number to handle irq update call, but it is not able to know
the irq number before irq installation, so move sde power event
call into kms post init to avoid unbalanced irq issues.
Change-Id: Id262b86f98299fbb9a51c9ccb8e68c7bde7f57ed
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
This changes takes pitches into account for alignment check
of destination writeback fb. As per HW recommendation
the stride needs to be a multiple of 256 bits.
Change-Id: Ib823a8d309f7ed579d701a4bf56772ce318fb1f5
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
The splash memory initialized by the bootloader needs
to be released after the first frame update. Add
memblock_free() call to release this memory that was
reserved during the kernel boot.
Change-Id: I463139a3f930dd9284d3ba9516714ead0c77cc02
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This change enables demura tap point capability in cwb.
Change-Id: Ie2e98ca721659c8151feeb36ff44244184ed5672
Signed-off-by: Yuchao Ma <quic_yuchaom@quicinc.com>
This change avoids sde error during fal10_veto override enablement
for targets with uidle disabled and early returns in such case.
Change-Id: I491952615d7b3cbd70d35b4a90ee8d27ab56c2ad
Signed-off-by: Yojana Juadi <quic_yjuadi@quicinc.com>
Kalama adds support for uidle fill level scaling to allow
fal10 mode for 90 and above fps use cases.
Pre-Kalama, the fill levels are clamped at 4-bit values supported
by the threshold registers. But to achieve the targeted 50us idle
time on fal10 modes with higher FPS use cases, we need fill levels
higher than 15 (max for 4 bit). The hardware change in Kalama
achieves by using a 5 bit scale factor in combination with the
programmed threshold values.
Change-Id: I638705355c03910a83e7d922b6fe48ab11c120a8
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
This change updates copyright description with correct
license marking as per the guidelines.
Change-Id: Ia74b721e78afcc7f8e88bcbccfcf15430111ec37
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
Destination scaler0 and scaler1 when operated in independent mode,
by two built-in independent displays the op_mode gets modified
concurrently and HW flushes new config. This leads to underruns
on both the displays. This change programs the op_mode
correctly to operate ds0 and ds1 independently.
Change-Id: I01a3d4a986e0e7166f8a38b4cf35981d3e434686
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Expand the DS enum and increase the DS max number
to support DS2 and DS3.
Change-Id: Iff8d591fece20528e30449c228db5cb2047cdded
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
Add support for detecting UBWC decoder version and program
UBWC configuration to hardware.
Change-Id: Ibe753d35ca46b069de8392c65a3b06131b7e238a
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
