Gráfico de commits

1629 Commits

Autor SHA1 Mensaje Fecha
Veera Sundaram Sankaran
b40c05519d disp: msm: sde: log vblank timestamp in eventlogs
Log the vblank timestamp during vblank callback. This will be
useful in calculating the precise difference between the vsync
while debugging. As part of the change, remove the vblank
counter logging in sde_crtc as it floods the logs with 4 entries
for each vblank request.

Change-Id: I6b532ad657581fb2a34318541acbd81a44858819
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-05-23 14:09:11 -07:00
Christina Oliveira
21ca2acab9 disp: msm: sde: add support for hwfence profiling
This change adds hwfence input and output fence profiling
registers and debugfs to enable them.
To enable input hw fences timestamps:
echo 0x1 > /d/dri/0/debug/hw_fence_status
To enable output hw fences timestamps:
echo 0x2 > /d/dri/0/debug/hw_fence_status
To enable both, input and output hw fences timestamps:
echo 0x3 > /d/dri/0/debug/hw_fence_status.

Change-Id: I269a38f3843a01ec8c0816890e50bb7d847a4ed9
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
2022-05-18 09:38:40 -07:00
Christina Oliveira
d2d060cf80 disp: msm: sde: add hw fence support for prog line count
This change adds support for triggering output
hw fence upon programmable line count.

Change-Id: Ie4b8252e4f9a448a8c11d17696b9bb0ded81b04b
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
2022-05-16 12:45:49 -07:00
Christina Oliveira
9a33a2a1fd disp: msm: sde: hw_fence update autorefresh disable sequence
This change updates the autorefresh disable sequence to manually
trigger output hw_fence during the transition. This is required
since on the last autorefresh frame HW will not trigger the output fence.

Change-Id: I6789fc6b51421524f88dcbdd1a063ae947646ae4
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
2022-05-16 12:45:27 -07:00
Christina Oliveira
5f554a52b9 disp: msm: sde: disable hw_fence for cmd/vid mode switch
This change disables hw_fences when a mode switch
from video to command mode or command to video mode
is ongoing.

Change-Id: I6f99226b59b381c6d2ff34a85753f8608080f546
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
2022-05-16 12:45:12 -07:00
Christina Oliveira
d3104b1f9f disp: msm: sde: add fence ready in event log
This change adds the value of hw-fence ready to
event logs for video and command modes.

Change-Id: I40a2e886a3b95e8853efcbdddf7fd9f6ce48eb9b
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
2022-05-16 12:44:59 -07:00
Christina Oliveira
0e20e27cc1 disp: msm: sde: adds mem mapping for hwfence ipcc reg
This change adds one-to-one memory mapping for the hwfence
ipcc register memory needed for hw fence feature.

Change-Id: I0e264183e02d0ed5f2254b409cc5e776d670f0dc
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
2022-05-16 12:44:45 -07:00
Christina Oliveira
640c8111d3 disp: msm: sde: add support for hw-fence feature
Starting mdss 9.0, dpu supports triggering
the frame fetch through hw-fencing. This change
adds support for this hw-fence feature.

Change-Id: Icc7d0b69fc2a51103d14612f5ac89b44a47ed826
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
2022-05-16 12:41:28 -07:00
qctecmdr
487e4ebec2 Merge "disp: msm: sde: add reg dma support for vig DE lpf" 2022-05-16 08:37:45 -07:00
qctecmdr
7f6a4cdee7 Merge "disp: msm: sde: add custom event to notify OPR, MISR value change" 2022-05-10 21:25:05 -07:00
qctecmdr
98d739db59 Merge "disp: msm: sde: toggle LLCC SCID for consecutive LLCC write" 2022-05-10 08:38:47 -07:00
Akshay Ashtunkar
9423445a34 disp: msm: sde: add custom event to notify OPR, MISR value change
This change collects the OPR, MISR values. If the values are
different than the previous then notify to client with custom event.

Change-Id: I2546439be1f665d90e6505d65283d28096bf7cdd
Signed-off-by: Akshay Ashtunkar <quic_akshayaa@quicinc.com>
2022-05-10 09:51:16 +05:30
Amine Najahi
d03f18c6b9 disp: msm: sde: toggle LLCC SCID for consecutive LLCC write
Toggle LLCC SCID for each consecutive LLCC write
operations and force read allocate when NSE bit
set.

Change-Id: Ice473cb126b627056b7346f142bc84c120e05f0b
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-05-09 17:07:58 -04:00
Renchao Liu
b56c45e4be disp: msm: sde: add reg dma support for vig DE lpf
This change adds reg dma support for vig DE lpf.

Change-Id: I9108046bb2afb987eec49224df4a45c37f9c27cd
Signed-off-by: Renchao Liu <quic_rencliu@quicinc.com>
2022-05-07 16:34:11 +08:00
qctecmdr
0384633caf Merge "disp: msm: sde: update vsync soure as part of post modeset" 2022-05-06 06:09:04 -07:00
qctecmdr
63a9b89055 Merge "disp: msm: sde: fix precise vsync feature check" 2022-05-06 01:23:21 -07:00
Narendra Muppalla
f014267f93 disp: msm: sde: update vsync soure as part of post modeset
This change updates vsync source as part of rc post modeset. For some
use cases like idlepc with DFPS, vsync could be configured for
previous fps and can cause timeouts during next frame.

Change-Id: I110fd958d2970eaca50ace0e72c4faea3fc64ce8
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
2022-05-03 15:02:54 -07:00
Nisarg Bhavsar
75aedb1c53 disp: msm: Address static analysis issues
Avoid various possible nullptr dereferences.
Addresses various issues highlighted by static analysis.

Change-Id: I36d34d610b37bf2799a7e34cd1de8b909b5c0ae4
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
2022-04-28 11:53:38 -04:00
Veera Sundaram Sankaran
2d889b43ea disp: msm: sde: fix precise vsync feature check
Check the precise vsync feature bit in sde hw catalog features
bitmap for checking the precise vsync feature and remove the
obsolete has_precise_vsync_ts variable.

Change-Id: I1f0cfabe5dcf387358548e8ff5ea0d65d4d7cecf
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-04-26 15:46:33 -07:00
qctecmdr
b0aa8dbb0f Merge "disp: msm: sde: add support for LLCC_DISP_1 SCID" 2022-04-26 13:11:31 -07:00
Amine Najahi
bffdc0271d disp: msm: sde: add support for LLCC_DISP_1 SCID
Currently only LLCC_DISP SCID is used to read and write to
system cache during static display use case.

This changes adds SCID LLCC_DISP_1 to allow each SCID to
have a dedicated function (read/write).

Change-Id: I5604ec1183d99a8492b005ec06ac94e5db60b5f7
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-04-26 10:29:29 -04:00
qctecmdr
2ed5675910 Merge "disp: msm: sde: convert system cache boolean to feature bit" 2022-04-26 06:38:24 -07:00
Amine Najahi
50092909c0 disp: msm: sde: convert system cache boolean to feature bit
Currently a boolean variable is used to track if the system
cache feature is enable for a particular SCID.

This change converts it to use a feature bit instead.

Change-Id: I8461fd9fb837b871c4ac5c67a9ab7613aadea7bb
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-04-25 16:33:00 -04:00
Amine Najahi
edd8be4319 disp: msm: sde: log SCID during LLCC activation
Add SCID to event log and debug print during LLCC activation.

Change-Id: Ib4c0a68506e9620ca42aba03db35c9ee21eda6dd
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-04-25 16:32:53 -04:00
Bruce Hoo
02e97873a2 disp: msm: merge flag of register and dbgbus
Merge reg_dump and dbgbus dump flag into dump_mode, and bring
back debugfs node "evtlog_dump" to keep flexible controlling
of evtlog.
Set in_mem option as default dump mode, since in_coredump
option will be enabled once HW recovery feature is enabled.

Change-Id: I75de1a69b01594b652479bf79201591ac0bf62e5
Signed-off-by: Bruce Hoo <quic_bingchua@quicinc.com>
2022-04-25 08:07:46 -07:00
qctecmdr
13d8ca3148 Merge "disp: msm: sde: change ubwc revision" 2022-04-22 23:08:47 -07:00
Amine Najahi
3cfd52c905 disp: msm: sde: enable vsync irq during sys cache read work
Currently, when doze mode is enabled the encoder off work
worker is started 1 ms after idle power collapse because of
aggressive idle-pc feature. This causes the system cache
worker to start after the clocks and vsync interrupt are disabled.

This change independently enables clocks and interrupts during
system cache work thread to decouple it from the encoder
off work sequence.

Change-Id: I8ed172b0e7c5c8e4e270e768434301d972e90eb9
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-04-20 13:23:06 -04:00
Shamika Joshi
b2f0c90aca disp: msm: sde: change ubwc revision
UBWC revision is in the expanded form, no need to process it again.

Change-Id: Ie4aafeea5459a76f325a07e58af1de5665fe45ba
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
2022-04-19 09:32:11 -07:00
qctecmdr
99e41b7489 Merge "disp: msm: sde: reset plane cache state on plane disable" 2022-04-11 16:47:35 -07:00
qctecmdr
97c6db4693 Merge "disp: msm: sde: use LLCC_DISP for static display usecase with cwb" 2022-04-10 07:19:01 -07:00
qctecmdr
efb465749b Merge "disp: msm: sde: handle SSPP system cache for multi-plane scenario" 2022-04-10 03:21:03 -07:00
qctecmdr
cb6ce492b5 Merge "disp: msm: sde: update HFC layer checks" 2022-04-09 16:51:07 -07:00
qctecmdr
95eb4d982c Merge "disp: msm: sde: add the DE lpf flag setting" 2022-04-09 13:24:42 -07:00
qctecmdr
6e5db7e5eb Merge "drm: msm: add spr by pass support" 2022-04-09 13:24:42 -07:00
Veera Sundaram Sankaran
c5121825bf disp: msm: sde: reset plane cache state on plane disable
Plane cache state is updated based on the crtc's cache state.
The plane is left with state cache state, if the particular plane
is not used in the subsequent frame by the same crtc. Reset the
plane cache state on plane disable and reset_custom_properties to
avoid this case.

Change-Id: Ic6d31567af23906e94c5404d1d366e030b9be199
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-04-06 10:51:24 -07:00
Veera Sundaram Sankaran
65b81f914e disp: msm: sde: use LLCC_DISP for static display usecase with cwb
Static display usecase uses concurrent writeback path to compose the
layers and updates the primary display in the next cycle with cwb
output. Use LLCC_DISP scid for system cache in cwb path, to keep it
in sync with the legacy static display path. Use LLCC_DISP_WB for
the offline-wb path. Expose the writeback connector cache property
only when either or both the cache types are enabled.

Change-Id: I8ca4b14828a14ce0bde829136fb4baef272166aa
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-04-06 10:51:24 -07:00
Veera Sundaram Sankaran
beeab715ac disp: msm: sde: enable LLCC_DISP_WB for kalama target
Add sde hw catalog change to enable LLCC_DISP_WB system cache, which
is used for 2-pass composition usecases with offline writeback path.

Change-Id: Ic320b95a6699e59c62fed41f7fb88c484d98ffd0
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-04-06 10:51:24 -07:00
Amine Najahi
05014b30d1 disp: msm: sde: handle SSPP system cache for multi-plane scenario
Currently, when CWB system cache use case is enabled and multiple planes
are used to fetch the LLCC data only one SSPP is programmed correctly.

This change ensures that whenever the fb_cache_flag is non 0, the SSPP
system cache gets reprogrammed.

Change-Id: Ic90eaae207f6221efb1fc8749093d8b44e092e44
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-04-04 07:07:49 -07:00
Rajesh kv
03aad2fdf9 disp: msm: sde: add line insertion support for sspp
Add line insertion support for sspp, this is used to support
display with external splitter. Line insertion logic checks
the difference between screen logical height and physical
height. If any difference is observed adds dummy and active
lines on screen.

Change-Id: Ieec322273df000a53fb39e05174c2d67c3c2da81
Signed-off-by: Rajesh kv <quic_kvrajesh@quicinc.com>
2022-04-01 09:35:03 +05:30
qctecmdr
fdcfe00b0b Merge "disp: msm: sde: drop suspend state if commit is skipped" 2022-03-31 17:23:16 -07:00
qctecmdr
0d5e286187 Merge "disp: msm: sde: shorter idle-pc duration in doze mode" 2022-03-31 17:23:15 -07:00
qctecmdr
e84f1b6640 Merge "disp: msm: sde: disable autorefresh on encoder disable" 2022-03-31 07:49:19 -07:00
Veera Sundaram Sankaran
3112cb87dd disp: msm: sde: fix sde_vbif_get_xin_status return value
sde_vbif_get_xin_status is expected to return true if client is idle
and false otherwise. Update the final return status based on this
expectation.

Change-Id: I3a9ff7c83cb5966ff5573b27e5c2e88423448199
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-03-29 12:16:17 -07:00
Veera Sundaram Sankaran
e50d08286f disp: msm: sde: disable autorefresh on encoder disable
Disable the autorefresh during encoder disable to avoid any
pending frame transfers while disabling. Additionally, handle
frame_done for new autorefresh frames to signal the fences and
proper accounting of pending_kickoff counter.

Change-Id: I8af114972b19ccdf0edab6b4c454ee90b4e8d8cf
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-03-29 10:41:46 -07:00
Yu Wu
6e050f641a disp: msm: dsi: Remove backlight operation during poms process
During POMS process, from vid to cmd or from cmd to vid, we both
see black screen, this is caused by backlight operation. Logically
display driver should not operate on backlight during POMS process.

Change-Id: I3bc76d6ed9ccee50f740c36cb276b6b103e7d43e
Signed-off-by: Yu Wu <quic_zwy@quicinc.com>
2022-03-28 00:36:32 -07:00
qctecmdr
cba5134cac Merge "disp: msm: sde: address static analysis issues" 2022-03-25 23:49:17 -07:00
Nisarg Bhavsar
4d8bf011d5 disp: msm: sde: address static analysis issues
Avoid various possible nullptr dereferences
and check validity of index before accessing
arrays. Addresses issues highlighted by
static analysis.

Change-Id: I5abfbc8c4cacb56e9decc3a6339ab0fa3a63b606
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
2022-03-25 13:26:33 -07:00
qctecmdr
89422fbde1 Merge "disp: msm: sde: enable llcc in AOD mode" 2022-03-25 12:06:36 -07:00
Govinda Rao K S
1928128776 disp: msm: sde: enable llcc in AOD mode
LLCC usage is currently limited to static display
configuration. With these changes, LLCC will be
enabled for always-on screen with Video mode.

Change-Id: I54cbb6f0aa6380819ca00e02ac8ffd1c01d07ede
Signed-off-by: Govinda Rao K S <quic_gkarikur@quicinc.com>
2022-03-25 09:09:42 +05:30
qctecmdr
51f0c1bd0b Merge "disp: msm: sde: install default value for panel_mode property" 2022-03-24 20:13:01 -07:00