When poms supported panel is booting up with video mode
rsc timers are not configured. Made changes to update rsc
timers configuration during bootup with video mode as well,
to avoid rsc stuck issues during poms switch.
Change-Id: I8c03b3e5483c17f73e3d8c6b57bd8d3eabb33b10
Signed-off-by: Andhavarapu Karthik <quic_kartkart@quicinc.com>
Dither, unsharp should not be enable when VLUT
is disabled. This change ties dither, unsharp to VLUT
enable/disable and not during init property.
Change-Id: Idfad899a13252b22104c9746c86f4e158d9b0980
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
Anti aging requires cwb capture for algorithm. This change adds
support for cwb capture with downscale. Dnsc block needs to be
disabled when cwb is disabled.
Change-Id: I52e3eb4442440e6c59eb96566b0f6af1fd10c973
Signed-off-by: Mitika Dodiya <quic_mdodiya@quicinc.com>
Changes to select particular dp_aux_switch based on board
requirements. Currently provision to support both fsa4480
and wcd939x as aux switches are provided.
Change-Id: Iafbee4d91d14aafb1e7a37ddfa2b1ea0d0e5e784
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Set topology override to cmdline topology before parsing timings so that
correct topology is set in mode.
Change-Id: I7ba371370c71516b436dbe5ec07064f7b54975bb
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Demura init property gets reapplied during first commit after resume.
However, first commit after resume is null commit and HFC correction
file will not be available during first commit.
This change marks error to warning for first commit after resume.
Change-Id: I01ec4bd977d60925d9b7a54076329c3becaa0b20
Signed-off-by: Sanskar Omar <quic_sansomar@quicinc.com>
In legacy POMS feature, there were separate timing nodes for
video and command mode. So, while calculating the total number
of modes, 1 extra mode is added for command mode if POMS feature
is enabled in video mode panel.
But as per the new design, this is clubbed into one timing node.
So, there is no separate mode for command mode. This change removes
the check to add 1 extra mode count otherwise it leads to null
pointer dereference while getting lm for this extra mode. Also
avoid overriding mode capability when POMS is enabled.
Change-Id: I73f3b89b22f566e40c88178f2af392214b1ada8d
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
In POMS use case while disabling the virtual encoder, the virt
reset function sets the current master to null. concurrently, if
there is a query from the DRM client for the current vsync count,
it returns a zero value. This results in the blocking of the
drm_crtc_funcs.disable_vblank function. since the vsync count
has been relocated to the virtual encoder, remove the physical
encoder structure.
Change-Id: Ie692df657b5a86b6b8915a15e9a070642243fcfb
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
In POMS use case, the handling of the wait for vsync event
completion coincides with the concurrent
drm_crtc_funcs.enable_vblank. This concurrency causes a vsync
event complete timeout while disabling the encoder. to fix this
concurrency problem, increment the vblank refcount in encoder
disable and release the vblank refcount in encoder enable.
Change-Id: I79671e4a2bafdd01a6b2523a80fe511bff23d6b6
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
In CWB use case along with suspend commit, the function
drm_crtc_funcs.get_vblank_counter returns a zero vsync count
value. This causes blocking of drm_crtc_funcs.disable_vblank,
leading to a wait for vsync timeout while disabling the encoder.
hence clear a cwb encoder mask in encoder disable and set it
while performing mode set.
Change-Id: Ic994aa0a86faf48e2b25955cf6fe12166fe9d328
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Introduce vsync count variable in virtual encoder structure
to keep the vsync count variable value in sync while performing
the poms. Consequently, this prevents the blocking of
drm_vblank_put and the invocation of
drm_crtc_funcs.disable_vblank.
Change-Id: I74903a89b17a8f46fb1b21338500553f36771dd0
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Currently revalidation of features happening for mode change(like
fps change, resolution change). This change limits revalidation
of feature only to resolution switch.
Change-Id: I3678e0e94eaad51e7b7a342eb451aa6329e8279d
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
In lower fps the scheduled off_work for idle pc race with
crtc_commit thread causing janks in display. This change
updates the time required to enter idle_pc based on frame
rate instead of default time. It also sets max and min bound
for optimized performance.
Change-Id: I514015361d6773156971dcc5801ed4b75d78db86
Signed-off-by: Yojana Juadi <quic_yjuadi@quicinc.com>
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
During PM suspend in dual display usecase, the power off commit to
turn off primary and secondary crtcs is done with only one
drm_atomic_state scheduled on primary crtc_commit thread. At the
same, touch events can happen on secondary panel, which will
run input_event_work and schedule the sde_enc->delayed_off_work
to turn off its enabled resources. There can be race between primary
crtc_commit thread which unregisters input_event, cancels
all the pending works before setting sde_enc->cur_master to NULL
and input_event_work_handler which schedules the delayed_off_work
without checking the input_event_handler state.
This change adds input handler unregister check before triggering
_sde_encoder_rc_early_wakeup.
Change-Id: If6de3d45ccda5d0b84065a1a76964c1ab00eeaa1
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Testing of the SPR feature shows IPC restore frames where partial update
programming is not applied. This is a result of the pre-IPC cached ROI
region being used for filtering of CRTC ROI changes.
Update the CRTC cached ROI logic to clear the cached ROI on IPC events.
This ensures color processing partial update logic handles the post IPC
frame with a clean state.
Change-Id: I4e337bd150d02e4c8934ca04c0d632d5ad71dd5d
Signed-off-by: Christopher Braga <quic_cbraga@quicinc.com>
When there is CPU processing delay between first INTR clear and
second INTR clear there is a chance that the second register
write might clear the next frames interrupts which will avoid
triggering the irq callbacks causing software hung. This
patch avoids such a scenario by removing such double clearing
of INTR registers.
Change-Id: I8407991769c69d2d2c691763240671d5f3c0416d
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
DPU driver registers core clock with MMRM driver for clock
mitigation policy. In the event that MMRM driver is not enabled
then mark dpu driver clock as non MMRM type.
Change-Id: Id4dd4a512c81ba54514171867852531f00604a66
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
In case of underflow/overflow IRQ storm, send panel dead event from
scheduled underflow and overflow workqueue handler.
Change-Id: Ic6cd6cbae097ea970a392fa99e30b3b620633d40
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
After triggering dynamic refresh, if there is any dsi_ctrl_isr, dynamic
refresh done status also gets cleared as part of it. Because of this,
wait4dynamic_refresh_done timeout error is seen even though dynamic
refresh is done successfully.
Change-Id: I39b42c60d15d9cb0557669f95ff2ed83989f9cd3
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
While transition from very low fps (1Hz) to higher fps (120Hz)
there will be a delay on first frame to take effect on
mode switch. In such cases if kickoff_timeout value is programmed
based on newer high fps wr_ptr_timeout can happen. To avoid this
update the kickoff timeout with respect to lower fps and reset
it back according to present fps once the mode switch commit is
done.
Change-Id: I08e1a68bb1e388a1bda8ef61d47e9eb4b2fc97fe
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Check that link clock is enabled before attempting to enable
stream clocks.
Avoids NOC errors when a disconnect is triggered while a modeset
operation is occurring.
Change-Id: I12d363261d4f36bf7d3149b77a917ecfa0e7b8ed
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
If cont splash is enabled, wait for autorefresh_status to be idle for
1 vsync in prepare kickoff. This patch also prevents entering to
rsc_solver_mode if autorefresh_status is busy.
Change-Id: Id7491361dae2482905e10a5a10e590d5f5b49e6f
Signed-off-by: Yojana Juadi <quic_yjuadi@quicinc.com>
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
This change stores the connector id before the connector
is set to NULL in post_disable.
Allows tracing through of a single connector's disable
flow in a MST scenario.
Change-Id: Ibf4079ea75c9e0643d0d9976289ab6983509ee93
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Partial update of SPR CFG 5 is showing intermittent odd
behavior. Move CFG 5 programming to AHB path to resolve
the issue.
Change-Id: I0719de9ea29ffe2f75c072053162133681a1b007
Signed-off-by: Christopher Braga <quic_cbraga@quicinc.com>
When wfd display is connected, qseed3 coefficient lut programming
is getting erased due to idle pc entry for wfd pipes. On idlepc
exit commit, plane properties are not reconfigured from userspace
since support is not present for writeback crtc. This patch
updates idle pc handling to avoid gdsc power off when writeback
crtc is connected and for CWB encoder gdsc power off will happen
on idle pc entry.
Change-Id: I7f75bf45089acaf1bd1b775351e05bcdcc89fc9e
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
