Commit-Graf

6 Incheckningar

Upphovsman SHA1 Meddelande Datum
Venkateswara Naralasetty
26099afe23 qcacmn: suspend/resume changes for WCN6450
Changes required for suspend/resume support for WCN6450

Change-Id: I4610f6bdb8de92f03884af6c07a5141dd27174be
CRs-Fixed: 3447469
2023-04-18 12:11:24 -07:00
Karthik Kantamneni
0562ed7a5e qcacmn: Code to init/deinit SOFTUMAC based Rhine architecture.
This code helps to initialize and deinitialize new SOFTUMAC
based Rhine architecture.

Change-Id: I374140ccb3b31e9351c6e683c77d81a5a876472a
CRs-Fixed: 3382913
2023-03-28 11:30:30 -07:00
Manikanta Pubbisetty
8d58a4e757 qcacmn: Add TX enqueue logic for WCN6450
Implement TX enqueue logic for WCN6450. There are no host facing
UMAC HW blocks in WCN6450. Driver enqueues all TX packets to
copy engine (CE) over the copy engine channel that is mapped to
HTT_DATA2_MSG_SVC service.

Changes are specific to WCN6450 and hence implement the logic
in the arch specific code.

Change-Id: Ia366a74b94a4e84c1d4c037c7a99093bb6739178
CRs-Fixed: 3381755
2023-03-16 11:19:41 -07:00
Manikanta Pubbisetty
6758a546bc qcacmn: Add TX descriptor changes for WCN6450
WCN6450 is a chip based on Rhine architecture. Unlike LI/BE targets,
chipsets based on Rhine (RH) do not have host facing UMAC HW blocks.
Their corresponding SRNG interfaces are also removed. The functionality
of these UMAC HW blocks is replaced with a software implementation in
the firmware. Communication between the driver and firmware will happen
over copy engine (CE).

Although there are no host facing UMAC HW blocks, the CE hardware used
in WCN6450 expects the host driver to use the TX descriptor (HW) format
of LI targets during TX packet enqueue. Therefore it is required to
create a new pool of TX descriptors (HW) pool for WCN6450 that is used
during TX.

The logic to create/free/init/deinit these descriptors is specific
to WCN6450/Rhine, therefore it is implemented in architecture specific
Rhine code.

Introduce new APIs in struct dp_arch_ops {} to allocate and free
arch specific TX descriptors. These ops will be no-op for LI/BE
architectures.

Also for Rhine targets, allocate/free other TX descriptors like TX EXT &
TSO descriptors as part of the arch APIs.

Change-Id: I452ac69143395881ab8580355a0f75571dc3e929
CRs-Fixed: 3381711
2023-03-16 09:30:15 -07:00
Karthik Kantamneni
2edb0c0388 qcacmn: Add RX handling for RHINE architecture
RHINE is soft UMAC based architecture which is not having
REO block, all the REO functionality will be implemented
in F.W and host level. Host will get the RX packets in
CE-RX rings in HTT format, to reap RX packets new HTT
messages will be extracted and parsed.

So implement RX handling based on new softumac architecture for RHINE.

Change-Id: If430dd017309e2b2a3eb5e27e1d8b58696abceb4
CRs-Fixed: 3382920
2023-03-14 01:41:05 -07:00
Karthik Kantamneni
29eb537def qcacmn: DP changes to add new RHINE arch specific files
This change introduces new RHINE architecture specific DP files.
RHINE is new SOFTUMAC based architecture, unlike LI/BE targets
all the HW UMAC functionality will be replaced with software base
UMAC functionality. So current RHINE arch specific implementation
is aligned to softumac based implementation.

Change-Id: I70baf11130afc07c5c85437d2343d0976ce0ea0a
CRs-Fixed: 3382880
2023-03-07 07:51:34 -08:00