提交線圖

12 次程式碼提交

作者 SHA1 備註 日期
Venkateswara Naralasetty
26099afe23 qcacmn: suspend/resume changes for WCN6450
Changes required for suspend/resume support for WCN6450

Change-Id: I4610f6bdb8de92f03884af6c07a5141dd27174be
CRs-Fixed: 3447469
2023-04-18 12:11:24 -07:00
Manikanta Pubbisetty
b5ac9ed64c qcacmn: Record hardware TX descriptor during enqueue for WCN6450
Record hardware TX descriptor history during TX enqueue for WCN6450
(Rhine hardware). This will aid in debugging data path issues.

Change-Id: I99c2a88ca161f89d529cba92692811fadee28938
CRs-Fixed: 3462090
2023-04-13 03:32:51 -07:00
Karthik Kantamneni
dd822c960f qcacmn: Add RX error handling support for RHINE
Handle RX error MSDUs received in normal RX path
in RHINE architecture.

Change-Id: I56a4ef2e52f5b0668436594ca55c1cb0d48f97be
CRs-Fixed: 3456495
2023-04-12 14:53:59 -07:00
Karthik Kantamneni
7d007a3edf qcacmn: Add RX ring based debug history support for RHINE
Add RX debug history support and first packet marking
after WOW for RHINE architecture based RX path.

Change-Id: Ife719bdc3e5031a63b3f97c5842a220caeda8ffd
CRs-Fixed: 3452940
2023-04-12 14:53:48 -07:00
Manikanta Pubbisetty
b5f74912c1 qcacmn: Add TX completion logic for WCN6450
In the case of WCN6450, WBM HW block is removed in the UMAC.
TX completions come via HTT messages. Add logic to handle
HTT TX completion messages from the firmware.

Changes are specific to WCN6450 and hence implement the logic
in the arch specific code.

Change-Id: I447020354ce26e8948e4b49648c434fb2ed302cd
CRs-Fixed: 3381814
2023-03-29 01:13:21 -07:00
Karthik Kantamneni
0562ed7a5e qcacmn: Code to init/deinit SOFTUMAC based Rhine architecture.
This code helps to initialize and deinitialize new SOFTUMAC
based Rhine architecture.

Change-Id: I374140ccb3b31e9351c6e683c77d81a5a876472a
CRs-Fixed: 3382913
2023-03-28 11:30:30 -07:00
Manikanta Pubbisetty
8d58a4e757 qcacmn: Add TX enqueue logic for WCN6450
Implement TX enqueue logic for WCN6450. There are no host facing
UMAC HW blocks in WCN6450. Driver enqueues all TX packets to
copy engine (CE) over the copy engine channel that is mapped to
HTT_DATA2_MSG_SVC service.

Changes are specific to WCN6450 and hence implement the logic
in the arch specific code.

Change-Id: Ia366a74b94a4e84c1d4c037c7a99093bb6739178
CRs-Fixed: 3381755
2023-03-16 11:19:41 -07:00
Manikanta Pubbisetty
cd50866740 qcacmn: Handle flow map/unmap HTT messages for WCN6450
In the case of WCN6450, sizes of the TX descriptor pools are not known
to the driver during load time. The sizes are shared by the firmware
post VDEV creation via HTT_T2H_MSG_TYPE_FLOW_POOL_MAP HTT message.
After the VDEV gets deleted in the firmware, a corresponding flow unmap
HTT message will be sent to the driver to clean up the TX descriptors
of a particular VDEV.

Add logic to handle the flow map/unmap HTT messages for WCN6450. These
messages are specific to WCN6450 and hence the logic is implemented in
arch specific HTT code.

Change-Id: I8edcabbec77abae2c238f487acb7a48b478fd149
CRs-Fixed: 3381751
2023-03-16 11:19:31 -07:00
Manikanta Pubbisetty
6758a546bc qcacmn: Add TX descriptor changes for WCN6450
WCN6450 is a chip based on Rhine architecture. Unlike LI/BE targets,
chipsets based on Rhine (RH) do not have host facing UMAC HW blocks.
Their corresponding SRNG interfaces are also removed. The functionality
of these UMAC HW blocks is replaced with a software implementation in
the firmware. Communication between the driver and firmware will happen
over copy engine (CE).

Although there are no host facing UMAC HW blocks, the CE hardware used
in WCN6450 expects the host driver to use the TX descriptor (HW) format
of LI targets during TX packet enqueue. Therefore it is required to
create a new pool of TX descriptors (HW) pool for WCN6450 that is used
during TX.

The logic to create/free/init/deinit these descriptors is specific
to WCN6450/Rhine, therefore it is implemented in architecture specific
Rhine code.

Introduce new APIs in struct dp_arch_ops {} to allocate and free
arch specific TX descriptors. These ops will be no-op for LI/BE
architectures.

Also for Rhine targets, allocate/free other TX descriptors like TX EXT &
TSO descriptors as part of the arch APIs.

Change-Id: I452ac69143395881ab8580355a0f75571dc3e929
CRs-Fixed: 3381711
2023-03-16 09:30:15 -07:00
Karthik Kantamneni
2edb0c0388 qcacmn: Add RX handling for RHINE architecture
RHINE is soft UMAC based architecture which is not having
REO block, all the REO functionality will be implemented
in F.W and host level. Host will get the RX packets in
CE-RX rings in HTT format, to reap RX packets new HTT
messages will be extracted and parsed.

So implement RX handling based on new softumac architecture for RHINE.

Change-Id: If430dd017309e2b2a3eb5e27e1d8b58696abceb4
CRs-Fixed: 3382920
2023-03-14 01:41:05 -07:00
Karthik Kantamneni
84731a352a qcacmn: RHINE architecture specific HTT changes
Add HTT changes which are specific to RHINE architecture.
Some of the changes like dedicated TX endpoint service,
fastpath implementation and few other message handling
is different in RHINE. Current change add support for
RHINE specific HTT implementation.

Change-Id: I90c2d1d66cdadc5935e6b819e3f19e635c45cb51
CRs-Fixed: 3382915
2023-03-08 17:24:42 -08:00
Karthik Kantamneni
29eb537def qcacmn: DP changes to add new RHINE arch specific files
This change introduces new RHINE architecture specific DP files.
RHINE is new SOFTUMAC based architecture, unlike LI/BE targets
all the HW UMAC functionality will be replaced with software base
UMAC functionality. So current RHINE arch specific implementation
is aligned to softumac based implementation.

Change-Id: I70baf11130afc07c5c85437d2343d0976ce0ea0a
CRs-Fixed: 3382880
2023-03-07 07:51:34 -08:00