提交線圖

1 次程式碼提交

作者 SHA1 備註 日期
Satya Rama Aditya Pinapala
0a93edbae6 disp: msm: dsi: rework DSI PLL to be configured within PHY
Change avoids clock framework APIs to configure the DSI PHY
PLL. It follows HW recommendation to set the byte and pclk
dividers.

Change-Id: I8c110f3997e4ec4c2eaa28778b70091855725ab8
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2021-01-12 23:49:11 -08:00