Change log level for unavailable slave pll from warn to debug
to avoid redundant logs as parrot supports only one DSI.
Change-Id: I200a2f382a1dca7035e4960d3bb0c877867f8ba8
Signed-off-by: Kashish Jain <quic_kashjain@quicinc.com>
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
Add dsiclk_sel support for both DPHY and CPHY, update pclk_div
calculation w.r.t dsiclk_sel as per HPG.
Change-Id: I573addd62c77d1c9f089b7aadf386cd2e579f442
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
Rename dsi_clk mux as dsiclk_sel to match the naming convention
with HPG.
Change-Id: I50671a78fccdd10d74d43fdf8ef4ede0c55fd09b
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
This change adds support for bypassing hw access in DSI PHY/PLL
drivers which enables the DSI driver to run on emulation
platforms that might be missing those modules.
Change-Id: I3e83155a79d60f2357606746214d776cefabd651
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Signed-off-by: Alex Danila <quic_eadanila@quicinc.com>
DSI PHY has various resets defined to reset analog, PLL and digital
portions. In current sequence, these resets happen after PLL is locked
which can result in introduction of jitter on PHY lanes.Reordering these
resets to happen before PLL is programmed to have intended clean start
of DSI PHY.
Change-Id: I4eb5c05ea0e6015a5447728b2845b49817411c50
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
Change adds the new files for DSI PHY version 5 and 4nm
DSI PLL.
Change-Id: I97712d6ce53a60a6fae1c8331b6ba9a5d17b8d34
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
