This change add support to program dual tfe configurations in
SHDR to create sync between two TFEs. This change is required
if MUP bit is used in SHDR mode.
CRs-Fixed: 3508184
Change-Id: I270f7fd8e3cac1f1e50c5f16e7cba2c5e9c2b74f
Signed-off-by: Ayush Kumar <quic_ayushkr@quicinc.com>
This change is to add support for error inducement in TFE HW.
CRs-Fixed: 3426117
Change-Id: I19a5e095bc84fa88c308640a1d490162698bb45f
Signed-off-by: Ayush Kumar <quic_ayushkr@quicinc.com>
In overlap SHDR, epoch irq from TFE need to configure in such
a way that request should be apply at epoch of shorter exposure frame
before start of the next frame of long exposure to make sure that
new settings should apply properly in time.
CRs-Fixed: 3396382
Change-Id: I1ddc3ce95c6d404a3f76a27cc58083e11b03bace
Signed-off-by: Ayush Kumar <quic_ayushkr@quicinc.com>
This change add support for activate and deactivate ISP device in the
link when dual trigger mode in the link is set.
CRs-Fixed: 3374385
Change-Id: Ib6d25ab295d613fa5cd3edf1780362476920d74d
Signed-off-by: Ayush Kumar <quic_ayushkr@quicinc.com>
Add support to skip HW operations (power/CCI) for
sensor nodes with "hw-no-ops" property. These nodes are
dummy entries since CSID reads data from a different sensor.
CRs-Fixed: 3150840
Change-Id: I6ceb3f9d2ea4f16abb9d5d2a6b89d5cb1d95c614
Signed-off-by: Shravan Nevatia <quic_snevatia@quicinc.com>
(cherry picked from commit 3deec40a9a58296f6f43d3cfe15b092e5a16c28b)
Add validation checks in CRE, ICP and TFE drivers
to avoid OOB and null ptr access issues.
CRs-Fixed: 3248380
Change-Id: Ic2c6bd41e34605a3291e6f50fe0fe94a0ab30523
Signed-off-by: Nirmal Abraham <quic_c_nabrah@quicinc.com>
(cherry picked from commit a63bcb668392e1271ab0d2f53a54736a54325828)
While we lookahead and merge the continuous reg settings to
burst, the packed setting len with uint8 data type may happen
overflow if the continuous reg setting count is larger than 255,
then some reg settings missed and lead to some sensor issues,
so modify the data type of len to avoid it.
CRs-Fixed: 3678429
Change-Id: I51a153d2340b84dd874ecd7bef6b3df1356611b0
Signed-off-by: chengxue <quic_chengxue@quicinc.com>
(cherry picked from commit aadcb5e66d37f556c570621e3b15e834601f074b)
When CCI drains its payload cmds in QUEUE because
of CPU scheduling delays from SW Driver side then
next successive transaction will endup in NACK ERROR.
To Fix this issue, Updating payload cmds to CCI QUEUE
is moved to Threaded irq so that Scheduling delays can
be minimized and avoid NACK Error.
CRs-Fixed: 3562709
Change-Id: I577a6531d692a4f202651e2dd5d4cf0684259b75
Signed-off-by: Lokesh Kumar Aakulu <quic_lkumar@quicinc.com>
(cherry picked from commit bcdafbc3c3afcbed75c2c469f26d8c483d0430d1)
This change limit the resolution for the single camera based on fuse.
Acquire will fail in case width is greater than the supported width.
CRs-Fixed: 3679491
Change-Id: I4f3e8dfdbe80aee994ca66f12bbbcdc7cda77676
Signed-off-by: Dharmender Sharma <quic_dharshar@quicinc.com>
Introduce Threshold IRQ and compose dynamically
allocated buffer with CCI BURST WRITE Commands
and finally write to the CCI HW register and
manage Threshold Interrupts in optimized way. So,
that SW Driver latencies will not affect the I2C
BURST WRITE functionality.
CRs-Fixed: 3562709
Change-Id: I5749ba3b61e28d8f2c1075f46f470f5a9c5bd6b5
Signed-off-by: Lokesh Kumar Aakulu <quic_lkumar@quicinc.com>
(cherry picked from commit 1e4f481db9076c766b7300bb65364a13a61247c1)
Add changes for cpas for raveline camera .
Create target specific header files for raveline.
CRs-Fixed: 3318758
Change-Id: Ib1bd54975a97bc4b09293cf8a82a1c3bbbeecb31
Signed-off-by: Pranav Sanwal <quic_psanwal@quicinc.com>
(cherry picked from commit fc03d26be204900d7e19054915b52fbd3353444f)
Updates board list of supported msm-mmrm boards to include volcono.
CRs-Fixed: 3671077
Signed-off-by: Alok Chauhan <quic_alokc@quicinc.com>
Change-Id: Ia5c26af59e029506d961052a4a4f9f8b3f0fef18
Integer pointer passed as a parameter to function
cam_irq_controller_register_dependent is used as an
array iterating over num_registers. This might corrupt
or misinterpret adjacent memory locations causing out
of bound access issues.
This change fixes this issue by passing an array of
size num_registers as a parameter to
cam_irq_controller_register_dependent. Also, initializes
struct dma_buf_map to 0.
CRs-Fixed: 3658797
Change-Id: I18260c9be4df77716f00c3f5980aeb506e35dcdc
Signed-off-by: Shivakumar Malke <quic_smalke@quicinc.com>
In case of null pointing addresses in payload at bufdone irq handling,
will lead to crash. This change will do proper sanity to avoid null
pointer access.
CRs-Fixed: 3634649
Change-Id: I4b988101001dfafdd4250eb75377d03a3a8474c2
Signed-off-by: Yash Upadhyay <quic_yupadhya@quicinc.com>
(cherry picked from commit 75ef1aef5d3b740a15eef8f5b60a453568ca5721)
In Mix SHDR use case, Camera switch to video mode is failing.
Reason is FCG configurations support not enabled for Cliffs.
So to fix this issue enabled FCG configuration for Cliffs.
CRs-Fixed: 3672728
Change-Id: I6cbc5db1d02c07bb4df422c4b07d6b7eca1df3c6
Signed-off-by: Dharmender Sharma <quic_dharshar@quicinc.com>
