Using individual flush functions for each active hw blk
is not scable-able for future use. Clean up the ops to merge
all flush functions into one and manage HW block id
with same API.
Change-Id: I62afbc51fa7d345b3a1f5721e5e09661a4215f7a
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Add support to configure the DPU pipeline to support VDC-m
topologies.
Change-Id: Ib8ce9a0eaeaa838759fb09cb2ee164d4765e4989
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
This change adds support for dsc using the 3d mux hw block.
The 3d_mux hw block merges the input from layer mixer before passing to
dsc block for compression.
Change-Id: I21544c33fff2c1e604c0ae712a036a127d25afcf
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Certain sub-blocks need to be enabled disabled dynamically on a
seemless mode switch (for ex. partial update) CWB is another example
where control path interface configuration needs to be dynamically
changed on enable/disable of concurrent writeback. Similarly
3d mux needs to be enabled/disabled for partial update use cases.
This change modfies the current api update_cwb_cfg and makes it
more generic and adds support to enable/disable only the 3d mux.
Change-Id: I5e5a6e78b0599f689cb2f83d0d626a5f392eff6e
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
This change introduces new ctl path api read_active_status to check
if a particular hw block is active or not in the current control path.
This is specially required in continuous splash use case when bootloader
has programmed certain blocks and the kernel driver tries to find
out the same configuration. This is used to ascertain which DSC block
is active in continuous splash case since DSC blocks are not tied to
mixer blocks.
Change-Id: I8dd590aa2dc764bd340727c166e1133ef9ce7af5
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
SDE HW from lahaina has moved the DSPP flush bits from CTL_FLUSH
to new CTL_DSPP_x_FLUSH registers. This change brings in
support for programming the new DSPP flush registers which
allow more fine-grained control over what sub-blocks within
each DSPP get flushed.
Change-Id: Ie16c9b153d607bd7627ba02480813ab588bbe2ea
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
CWB, DP and WB displays tear down sequence must reset
3d_merge, ctl, pingpong_binding, etc. MDP HW
blocks. This change fixes the tear down
sequence register programming. It also moves flush
sw reset before encoder_disable call. That allows
CWB tear down to update the flush configuration
on primary ctl path.
Change-Id: I21c521b39456af4144cf836c65d46a25c985f51d
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Get controller scheduler status at each vsync to verify
pending frame status.
Change-Id: I01401a57b68828294299977a7be7e796d07c7472
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
This change brings msm display driver including sde,
dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel
project. It is first source code snapshot from base kernel project.
Change-Id: Iec864c064ce5ea04e170f24414c728684002f284
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
