Update sde_drm.h header to use the display techpack path for
kernel-5.4.
Change-Id: I2b7dcbbde8128eece7a2a8a652f9f7c427b38110
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Currently, for every DP hardware register read/write, there
is a string comparison to determine the execution mode. This
adds up an extra delay while powering up/down which does a
large number of register reads and writes. During stress
testing and automation, this can cause an issue resulting
in failures. Remove the unnecessary delays by using common
APIs for register reads and writes. Switch these APIs only
in case of execution mode change.
Change-Id: I9403873a29b3466c606297b2aa386d0885bb2dc7
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Add the colorspace property for DP controller for MSM. Also, change
the default method to send the colorimetry information to the sink
from MISC bits of MSA to VSC SDP packets if the sink supports it. This
helps to avoid dynamic switches between the packet types for sending
the colorimetry information during BT2020 and DCI-P3 use-cases.
Change-Id: I7ddf879a187b023fcf7404d64028e4d19b031119
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Currently a lot of information is packed into the HDR data structure of
the catalog panel making it difficult to individually control the
parameters like colorimetry and other information sent using
VSC SDP packets.
Break up the structure into individual VSC SDP colorimetry, HDR
infoframe and DHDR VSIF packets.
This makes it easier to control each of these parameters independently.
For example, when only the colorspace is changed its sufficient to
update only the VSC SDP colorimetry packets.
Also align these packets with the upstream DP helper header defines.
Change-Id: Ia208f30a480fd203192624fe4f3d99c1c89350dc
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Update the PLL and PHY power on and clock set sequence as per
the hardware recommendations. Move the post link clock phy enable
part to the catalog so that it can be programmed after enabling
link clock.
Change-Id: I9b3b49e5a9ac93bebcb1cb7da63b715a8d5ed85c
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Update the DP controller and PHY programming according to
the new hardware recommendations.
CRs-Fixed: 2458753
Change-Id: I1bce5915ba6ebbb250cc5c4aac907b0b287eece7
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
This change brings msm display driver including sde,
dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel
project. It is first source code snapshot from base kernel project.
Change-Id: Iec864c064ce5ea04e170f24414c728684002f284
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
