Move all the individual boolean flags from HW catalog into a
"features" bitmap. These flags are used to specify support of
various target specific features.
Change-Id: I2334b3b873f3737f91bbae4ef576408247710156
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
Remove memblock_free api, since currently is not
part of the ack tree. This prevents modpost compilation
errors for the display driver.
Change-Id: I8f657a123fbecc5d4b029d511b8d08fec2293f0c
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Pass full state to crtc, plane, and connector atomic functions and retrieve
drm_crtc/plane/connector_state within the atomic function. Additionally,
the plane atomic update function is used as an upstream hook as well as
locally called in the plane restore path. To ensure both paths are functional,
introduce a plane atomic update version which takes in drm_plane_state
keeping with the previous parameter expectations.
Change-Id: Ia295935dd81ea8680a347eba0929e209d93ae830
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Include of_common header file explicitly to use
of_fdt_get_ddrtype().
Change-Id: Idd814d6188d585b2d0ecd6935f3260a79d15401b
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
After adapting dma buf api's these references and
paths are unusable. Clean it up.
Change-Id: Id6fa76945132e312e8bacf6e430633b0db9e48a3
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Domain attributes has been deprecated on 5.14 kernel, so replace
msm_smmu_set_attribute with qcom_iommu_enable_s1_translations.
Change-Id: I1bf2d5ee089a418eb73605327e82b2e26bd6bada
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Commit b67da33a6307 ("trigger tx_wait if panel
resolution switch") increases the mode switch latency.
Alternatively, single buffer tear check registers can be
updated when vsync_in is disabled. It allows mode switch
frame trigger as posted start frame trigger.
Change-Id: I8068736b2ea01f6e4160e765fc39d7fc2a8590c9
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
During display encoder disable, reset the dsc control
mux configuration during null commit to ensure dsc hw
blocks are cleanly freed up.
Change-Id: I02e2f074450e4d7b49dc8fec14777f380786c63e
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
While hw resources allocation for an active display during modeset, avoid
dsc hw allocation switch by finding which dsc encoders are allocated
previously and allocate same dsc hw encoders. This helps in fixing underrun
issues in below scenario of dual display power ON/OFF.
Use case: Dual DSI display setup, both are DSC enabled, primary in video mode.
--> when both displays are in powered off, all hw block are free.
--> enable second dsi display
Since LM 0/1 marked for primary, LM 2/3 allocated along with DSC 0/1
--> enable primary display
LM 0/1 allocated with DSC 2/3 encoders
--> Now power off secondary DSI
DSC 0/1 are freed up
--> Immediate modeset on primary, DSC allocation switched
LM 0/1 and DSC 0/1 allocated. DSC 2/3 are freed up as per RM but
decoupling DSC 2/3 blocks with respective pingpong or intf is not done.
This is causing underruns on primary.
Tracking which DSC blocks are freed during resource switch and programming the
respective DSC control mux configuration is not feasible and not scalable as
any other display can allocate those blocks and would require synchronizing
across display threads. So approach taken is avoid dsc resource switch itself.
Change-Id: I7f740722a52266740c4b168edc0c619e3cf68989
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Add new properties to support dynamically turning on and off digital
dimming and setting new minimum backlight.
Change-Id: I3b94190877d556768ba2c92ec59432dec44de0de
Signed-off-by: Ping Li <pingli@codeaurora.org>
Trigger tx_wait if command mode panel resolution
switches during mode switch to avoid early single buffer
tear check programming.
Change-Id: Ib747df8250c714248a44b596c2c8aeef006ea4fc
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Userspace module may not trigger the atomic check and it
can cause the commit failure. In such case, always reserve
the minimum core clock rate on mmrm module for built-in
displays to avoid the power ON failure.
Change-Id: Iafd92a7b7d1b35befe70b041cbedaec2add40de4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
If an external display, such as DP, requests for the available
resources, resource manager (RM) will provide a count of all unused
mixers. If the primary/secondary display(s) are not active, the RM
will report the associated preferred mixers as free resources.
However, RM will not allow preferred mixers to be allocated to other
displays. DP driver could look at these available resources and assume
a high resolution mode is possible and fail during resource allocation.
This change updates the available resources info API to account for
primary/secondary preferences while exposing available resources.
Change-Id: I134a1047f24ac9f1fcee695aa14a1d3e43c1571f
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
MDSS INTF HW block does not generate vsync if controller
turns off the link clock prematurely. This leads to
frame trigger timeout and SDE driver triggers the retire
fence after 84ms to recover gracefully. A client may switch
source pipe from one CTL path to another CTL path based
on delayed retire fence. It can lead to other ctl path
hang. This can be resolved by resetting the lm blend
stages for each missing vsync frame trigger.
Change-Id: I5a6ed03afbdad83d8fd6decc593d39e04bef62e4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Noise and attenuation layers are full screen layers. Top left coordinates
are not cleared in some use cases when same blend stage is assigned to
noise and attenuation layers. This change sets top left coordinates of noise
and attenuation layers.
Change-Id: I6af7a38d011d0bb642dc3d8a4aff338075524906
Signed-off-by: Anjaneya Prasad Musunuri <aprasad@codeaurora.org>
When disabling an encoder with multiple physical encoders, the
intf mux must be cleared on all interfaces. Currently only the master
physical encoder is being cleared, leading to possible DSI
underflow errors. This change ensures that the mux is cleared
on all interface blocks.
Change-Id: Idb1b96fd65545e3599100e70ace22bc3837d7233
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
In the current code for finding the qsync min fps for a
mode, entire mode list is iterated which involves acquiring
dsi display_lock. During conn tx debugfs commands, if
qsync min fps is required, we try to acquire dsi
display_lock twice which results in hang state. This change
adds qsync min fps value in dsi_display_mode_priv_info
struct in order to get the qsync fps from the
msm_display_mode present in connector state instead of
looping through all the modes to find the mode qsync fps.
Change-Id: Ifded40d1f12462bb50fc7bdafb746ae5b8d9512a
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Dummy mixers for dedicated concurrent writeback can be allocated
as valid mixers. However, they should only be allocated for DCWB
usecases. Allocating these virtual resources incorrectly can lead
to underrun on external monitors. These dummy mixers should not
be tracked as available resources and exposed to dp for
mode validation.
Change-Id: I04f583d5b722e0a384a5446e3a8a2313a338aa12
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
In the current code, vmlock is always acquired in check
phase even if there is no transition between vm's. This
might result in janks if vmlock is held concurrently by
other processes such as backlight update. This change
ensures that vmlock is held only if there is a valid
transition request between vm's in check phase.
[cohens@codeauarora.org] Resolved trivial merge conflict
and refactored the code to reduce the code complexity.
Change-Id: I022f04c19ba04fdd5494580cc1436747620b9354
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
To ensure that set merge_mode after vlut and hist enable, move merge_mode
enable from ltm_init to ltm_vlut.
Redefine the OP_MASK of LTM_INIT_ENABLE and LTM_VLUT_ENABLE, in order to
write the merge_mode bits correctly.
Change-Id: I5258e7f545e265b114098e46d31986274127e962
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Yuchao Ma <yuchaom@codeaurora.org>
Current logic will unnecessarily call backlight update
twice in cases where backlight level is changing. When
this happens, there is a potential delay waiting for the
first command to complete before sending the second
backlight update with the same value. This change removes
one backlight call and now only calls update if the
property is marked as dirty.
Change-Id: I260f0d73b3a5af9ced7ae261d247595f965a8d9e
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
With this change, the IB vote will be based on the following:
IB = AB_aggregated / number of DDR Channels / DRAM efficiency factor
Number of DDR Channels and DRAM efficiency factor are now device tree
properties which can be modified and parsed at boot up.
Change-Id: I298043807150faec1cbc0d74eefcdd1a534b460a
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
In concurrent display usecases, dma_fence_array signaled op
can be called early which sets SIGNALED_BIT on spec fence, but
irq_dma_fence_array_work is not scheduled yet which clears the
PENDING_ERROR in dma_fence. Add changes to treat pending_error
with signaled cases as non fatal.
Change-Id: I3a59032345b8c6d1488e947e74985ed929112d1c
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
This change allows the commit in preclose to be attempted a
number of times in the event that the return value is -ERESTARTSYS.
This can happen if there is some timing delay which is preventing
the commit to go through completely and an error code is returned.
Change-Id: I26d85d777be182bc153532d7c06f816c934783a4
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This change resets panel_dead property at the end of dsi bridge post disable.
Currently as part of the ESD recvoery sequence, dsi_bridge_enable resets this
property, but WD vsync source is selected before this point based on the older
panel_dead status. With this change, panel_dead will be in a proper state and
the correct vsync source will be selected during recovery.
Change-Id: I6d614113cfb0ae8a857974bb4d4f8ceb5988a0c8
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This reverts commit 3617430855.
This change will re-enable qseed programming through lutdma.
Change-Id: I57b897088eeccddc63ee010e296b5d4622d27a9f
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Current DSC intial line calculation is giving extra line on top of
recommended value from systems since number of active soft slices
considered is wrong. Fix the number or usage of active soft slices
in an encoder to align dsc initial line with recommended setting.
Change-Id: I321260e22b7824b8c481a55b54831ce9535661cc
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Update dsc configuration and pps programming for 422 and
420 encoding as per the DSC hardware spec.
Change-Id: I4251614cdcd550ed724b1d0dba4846cada4b5392
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Bottom start must be lesser than display height by at least
one line.
Change-Id: I36fbf68ee6733c020f235dca04c4b00c1e5a2312
Signed-off-by: Anjaneya Prasad Musunuri <aprasad@codeaurora.org>
Existing LUTDMA hardware runs into issues when an odd number of
LUTDMA absolute address writes are executed before a GDSC power
collapse. Update LUTDMA logic to force absolute write payloads to
always contain an even number of writes.
Change-Id: I476feeab550f4b176d0adccaa5f2d38041e87657
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
Add a utility function to check if HW has been handed over to
another VM.
Change-Id: Ic36ca1e7f15f7608e69d69fc3f4e7ad40be15704
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
