For qca6750, update the SHADOW REGISTER OFFSET value and
fix the compilation issue.
Change-Id: Ic4b44c1c40e62ddcc50c0a66d37c0663a70b5c54
CRs-Fixed: 2633044
Write TID-no correctly for DSCP-value if
2 consecutive registers are needed to configure
the mapping.
Change-Id: I857f95e2d1bda0214a32b2802f1dcc460be87085
In current monitor status ring implementation,
on pdev_attach, (srng->num_entires – 1) entries
(to keep one entry slot between hp and tp)
are replenished and last entry is not replenished to HW.
With qcn9000 monitor mode HW enhancements, status and destination ring
can be made lock-stepped.
for qcn9000 lock step is achieved by making monitor status ring
follow the monitor destination reap for a PPDU
However in existing flow during attach monitor status replenish logic
do not fill last entry but is filled up during first subsequent reap.
for first ppdu, i.e. after reaping destination ring,
when status ring is reaped, as first entry (hp = srng->num_entires – 1)
in status ring is NULL, so lock-stepping is not achieved.
To address this issue for qcn9000 as well as HK:
a. Replenish last entry in monitor status ring during attach
b. Modify src srng peek API to peek it from hp+1 entry
c. Introduce new HAL API get cur desc and move next
CRs-Fixed: 2626049
Change-Id: I7da6cd6006243cbca2151da22a31a6f5ed0015f3
Intercept monitor destination path for NDPA frames,
use it to generate noack frames for tx capture.
Change-Id: Ia54196bd84729a7863954b6deec7e02b52f23556
CRs-Fixed: 2605672
Handle minidump logging using dynamic
configurablity options. Data structures
to be logged in minidump can be configured
using internal INI file.
Change-Id: I99f12b3f98c4a9c0e15c3e5d611019e6b8d0909a
Maintain a history of the register writes which
have failed. The failure of register write is
determined by reading back the register after
writing a value to that register. If the read
value does not match the value which was written
then it is termed as a failed register write.
Change-Id: Ic3423c2cbd74bf498c0d3dd8ee7ce4231054541a
CRs-Fixed: 2624475
Sometimes the register write in windowed region
are not going through, thereby retaining the
previous value, which can be incorrect for a
certain mode of operation for the driver.
This kind of incorrect register values, due to
a register write not succeeding, can lead to
unwanted issues. Also the simple logging of
any such occcurence can be over-written in the
logs, thereby going unnoticed.
Add a HAL level statistics to maintain the
count of such failed register writes.
Change-Id: Ib5e98705c23f0c916cb85f518576663710eb30e0
CRs-Fixed: 2611839
wifi load failed due to unknown symbol in qca_ol
Add export symbol inside compile time macro
Change-Id: If1bb24084a6f95678b51bb85aaa0b8a87df3d50b
CRs-Fixed: 2621904
Use static window for accessing UMAC and CE register in qca6750. For
UMAC and CE register access, separate static window is mapped. Host
accesses these registers using relative offset to window address.
Change-Id: I7940336579553f05a11f1379f635689d08508c56
CRs-Fixed: 2617684
Command ring is now renamed to credit ring on QCN9000
and used for credit based flow.
Renaming the ring to give meaningful name.
Change-Id: I726aed19477fcfb256e4e0cca8ddb9389035b58c
CRs-Fixed: 2562640
Update CE registers offset during hal srng configuration
and configure CE IRQ for qcac6750.
Change-Id: I4fd3d37783361f0029c7ef80e32425f8790d1250
CRs-Fixed: 2617699
For qcn9000, As part HW enhancements, PPDU_ID is sent
in reo_entrance_ring descriptor instead of RX_MPDU_START
tlv. Add support to read ppdu id from descriptor.
Modify existing hal API hal_rx_hw_desc_get_ppduid_get ()
arguments to pass RxDMA ring HW descriptor.
Usage:
a. Use hal_rx_hw_desc_get_ppduid_get () -
to get ppdu id from rx_tlv_hdr or hw descriptor based on target.
for qcn9000, this API gets ppdu_id from HW descriptor,
for other platforms, gets ppdu_id from rx_tv_hdr
b. Use hal_rx_get_ppdu_id () - to get ppdu_id from rx_tlv_hdr
Change-Id: I5838227c12cde50cbb2a9da7a0d8056b8b9b7ef5
Move flow learning and operation HAL macros from header file hal_rx_flow.h
to hal_rx_flow.c.
1) hal_rx_flow.c conditionally compiled in based on the feature
2) Function implementations are too big to be defined in hal_rx_flow.h
Replicate hal_rx_flow_setup_fse specific to FISA Flow programming.
Implement function to dump the FT entries.
Change-Id: I7db943495eecfc064c4b696939da83d1d8ed9280
CRs-Fixed: 2599917
Added new qca5018 hal folder to add ipq5018 specific changes.
This includes interface files to access ipq5018 hal registers.
Change-Id: I7e19dc7c8719fa175695b268dc904fb4521a3330
8074 and QCN9000 coexist, so make hal_rx_msdu_packet_metadata_get()
as chip specific
Change-Id: I5b0b5e7f8915d12d4b267d5f07b03b47bb49a83f
CRs-Fixed: 2595314
Move HAL_RX_MSDU_END_DA_IDX_GET macros to chip specific header file.
Fixing compilation failure for 6490 and 6750.
hal_rx_msdu_packet_metadata_get_generic need not be chip specific,
macros defining the function are already chip specific.
Change-Id: I940a289662bdeddfbf99fae2a80d7796334832e7
CRs-Fixed: 2595314
Rather than extracting msdu end pkt tlv information per field basis
during fast data path, extract msdu end pkt tlv information at once
and store in local structure.
Change-Id: I0877ba4f824d480cc0851c72090f010852d0d203
Add a framework to configure varying buffer size for both data and monitor
buffers.
For example, with this framework, the user can configure 2K SKB for Data
buffers, monitor status rings, monitor descriptor rings, monitor
destination rings and 4K SKB for monitor buffers through compile time.
Change-Id: I212d04ff6907e71e9c80b69834aa07ecc6db4d2e
CRs-Fixed: 2604646
fix the issue for block ack/ack for tx capture mode.
1. Hanndle BAR frame.
2. set rate for ACK frame.
3. Check block ack session and use block ack if block
ack session is established.
4. no ACK for broadcast probe request.
5. not ack if the ack policy is set to no ack in qos control.
Change-Id: I4f22c1c976334978fb971b42319fb3a6e43a00c2
Define shadow register value as 0 in else case where none
of the chips supporting SHADOW configuration are enabled. This
is needed for low memory configuration profiles where
QCN9000 and QCA6290 are undefined.
Change-Id: I6281568e830b506707aeb96d3ea03811cc1de8a7
Force wake request is sent before register write. If this req
fails check if FW is down or host is in recovery before
asserting.
Change-Id: I6d31b1f95b68ae4e462f59ed32ed933de55cacae
CRs-Fixed: 2601364
Add monitor mode support to capture packets over 6GHz frequencies by
getting capture frequency from pdev.
Change freq type to qdf_freq_t.
Change-Id: I7b6edc43e254dc98a3c2939c369874bec9d16ddd
CRs-Fixed: 2568970
the current HAL API is to read the WBM internal error
bit from the wbm release ring descriptor is always taking
HKv1 HW structure. But the wbm_internal_error bit
placement has changed from HKv2, for this reason we have
to use target specific HAL API.
Change-Id: I44789180754ca21ae59650b6d8620321a1f12569
Channel Frequency Response(CFR) feature requires PPDU information
for correlation with CFR data. Host subscribes for the relevant PPDU
status TLVs via the Host RX monitor status ring. During monitor status
ring reap, all information needed for CFR correlation is accumulated
in a HAL PPDU structure and delivered to WDI event subscribers.
Change-Id: I3662b60375cb8886447a2fba3efead6a1ef3a98d
CRs-Fixed: 2593408
Link descriptor were getting freed by the pointer
of the previous freed link descriptor. This patch
fixes by copying the address of the current in a
local descriptor info and using it to free the
current.
Change-Id: I95e137ba5b1f0ad21b0e6fb39f6671e1d5b65ba6
CRs-Fixed: 2577624
Block ack and ack frame is composed and sent to up
layer after a unicast packet to AP is received for
tx capture feature.
Change-Id: I4b6bb35fa093432539d15d09a93f85a8ec700b34
As per the REO logic, if a packet is received with
SN <= current SN, then it will be treated as a 2K jump
error or OOR and the packet in consideration will be
dropped by REO. For NON-BA case this case will be
treated as 2k-jump error.
For the NON-BA case, the packets with SN <= current SN
should not be dropped.
The current REO configuration, sets the BA window size
to 2 for NON-BA case, which in turn enables 2k-jump
detection.
For configuring the REO to not drop packets with previous
SN, we need not set the BA window size to 2, thereby
disabling the 2k-jump check for NON-BA case.
A. SN = 1, 2, 3, 4, 2096, …
(good case, as long as the SN is within 2K range)
B. SN = 3, 5, 2
(3, 5 are good packet, 2 is bad packet and will
be dropped to ‘2K error’ with error code = 2K error.)
(note that this is for non-BA session, for BA session,
we detect SN as either
2K error or OOR error based on SN and window size).
After this change, we will treat this as a good packet.
C. SN = 1, 1, 1, 1, with duplicate detect enabled – these are duplicate
packets and will be dropped to ‘DD queue’ with
error code = DD
(No change)
D. SN = 1, 1, 1, 1, with duplicate detect disabled – packets will be
dropped to ‘2K error’ with error code = 2K error.
After this change, we will treat this as a good packet.
Skip the setting of BA window size to 2 for aggregated
packets in NON BA case.
CRs-Fixed: 2580605
Change-Id: I19d5eced7c8730a9c3820fd6fc69923d2a98263a
sw_frame_group_id decides process for frame. USER_STATS tlv case uses
sw_frame_group_id to add qos_null frame control to rx_status.
Change-Id: Ia3da8dbe4fc4c2d0f21fa8864e6b4e87170ba8f6
When SAP do connection with first Ref-STA or dis-connection with
last Ref_STA, wlan host need to re-configure REO Dst ring control
register. one of the register offset is 0xA38004, host need to write
remap window register (offset 0x310C) with value 0x14 first, but
sometimes this remap window writing not work, so just use the remap
window value 0x3F left by last writing, final Dst register offset will
be 0x1FB8004 which is out of valid range.
Find that if we read back the remap window after writing is done,
remap window writing failure issue is gone. as a WAR, check register
writing result for this specific register REO_R0_DST_RING_CTRL_IX_0
always before root caused.
Change-Id: I8d385a0f974ff37bdd867d2ec946f2f46f6eff32
CRs-Fixed: 2570728
Write into hal register using three floating windows instead of one.
This change is done to avoid frequent window changes for writing into
DP and CE registers. Instead 3 windows are used. One window is statically
mapped to CE block and another window is mapped statically to DP block.
Due to this design there is no need to change the window register to
write into these blocks and write can be done on corresponding window
with single iowrite32. Similar loginc is used for ioread32.
Also modified the hp_addr and tp_addr in initialisation stage so that
hal_write will not have multiple if checks.
Change-Id: Ibb99ec4da7f63323082e46a28afbe90e1f555545
CRs-fixed: 2507441
1. Add hif_force_wake_request API to wake the
mhi and umac before reading/writing the memory region
greater than BAR+4K.
2. Add hif_force_wake_release API to release the
PCIE_PCIE_LOCAL_REG_PCIE_SOC_WAKE_PCIE_LOCAL_REG so the
umac can power collapse again at a later point of time.
3. Add pci stats to dump the force wake status.
Change-Id: Ic6d5463ea0cdb28d9144be61da55e43033b53298
CRs-Fixed: 2478052
Increase the force wake timeout to 100ms for
debug builds as mhi requires 100ms to
wake up.
Change-Id: Ida0b1287a86a5a97fd2d9c80fee4e677eea86cbe
CRs-Fixed: 2552815
a. Add new macro HAL_REG_WRITE_CONFIRM to check register writing result,
enable register writing result check when do REO DST ring remap for
IPA.
b. only enable register writing result check when macro
HAL_REGISTER_WRITE_DEBUG is configured.
Change-Id: Ib52e6b0d689ccf714876b3978fa8e356f652d25e
CRs-Fixed: 2557252
Add debugging infrastructure to record every event posted to reo
command ring. The infrastructure maintains the record of the last
64 events posted to the ring.
Change-Id: Id56fc352050eb664a64b0abb767f3b4a6b4c3aa3
CRs-Fixed: 2552822
Added change to modify ce flags for Pine.
Also made changes in window enable bit
Change-Id: Id080be53d14450cb6d9376fc810177bce26a2869
CRs-fixed: 2507441
The reo destination ctrl registers
HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR and
HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR are used for mapping
msdu packets to different reo rings.
For QCA6390,
reo remap values varied from 0 - 7 so every 3 bits in
the register were used to map to a particular reo ring.
For QCA6490,
reo remap values vary from 0 - 9 as two extra reo rings are
added so we are using 4 bits in the register to map to a
particular reo ring.
Use the macros directly provided in the header files
to map reo rings.
Change-Id: I6d64266d3b388b3453b7df959048e3d693cf0a40
CRs-Fixed: 2544102
If CNSS platform driver and wlan host driver try to write
window register at the same time, conflict happened which then
register write failed.
Use the window register lock shared from CNSS driver to avoid
the conflict.
Change-Id: Iccc4e60e4f5eed995ec6aa53b024f3f96a2619a0
CRs-Fixed: 2534408
