Sim panels are not working well with video mode, parse panel ack
disabled property to fix sim video mode identification issue.
Change-Id: Ife3b533d5a6db97618459dacf1f7ce8d3fc896bf
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
sde_vbif_get_xin_status is expected to return true if client is idle
and false otherwise. Update the final return status based on this
expectation.
Change-Id: I3a9ff7c83cb5966ff5573b27e5c2e88423448199
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Disable the autorefresh during encoder disable to avoid any
pending frame transfers while disabling. Additionally, handle
frame_done for new autorefresh frames to signal the fences and
proper accounting of pending_kickoff counter.
Change-Id: I8af114972b19ccdf0edab6b4c454ee90b4e8d8cf
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
During POMS process, from vid to cmd or from cmd to vid, we both
see black screen, this is caused by backlight operation. Logically
display driver should not operate on backlight during POMS process.
Change-Id: I3bc76d6ed9ccee50f740c36cb276b6b103e7d43e
Signed-off-by: Yu Wu <quic_zwy@quicinc.com>
Avoid various possible nullptr dereferences
and check validity of index before accessing
arrays. Addresses issues highlighted by
static analysis.
Change-Id: I5abfbc8c4cacb56e9decc3a6339ab0fa3a63b606
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
LLCC usage is currently limited to static display
configuration. With these changes, LLCC will be
enabled for always-on screen with Video mode.
Change-Id: I54cbb6f0aa6380819ca00e02ac8ffd1c01d07ede
Signed-off-by: Govinda Rao K S <quic_gkarikur@quicinc.com>
Remove hardcoding LLCC use case id and use catalog information
to decide which system cache section to use.
Change-Id: I9748ca1f3569db0cf77689af296def0759fe94cc
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
This change adds a connector OP, that will be used to update frame
transfer time dynamically at the request from user space.
It also adds parsing for new device tree entries that set the minimum
and maximum trasnfer times on a mode basis. These min and max transfer
times are also published to userspace through the connector mode info
capabilities blob.
Change-Id: I12aedf96a51ff7feb2c5b3b1353d3c4ec8dcb068
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Refactor the function '_sde_encoder_phys_wb_update_cwb_flush' to
reduce its complexity.
Change-Id: I91b5fd5409617d06c3c17799d6af128578c3ba16
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Add DSI CTL MISR support for ctl 2.2 version. Reuse the same
debugfs nodes to setup/collect misr.
Change-Id: I3d8dfab093659ce53817d9511999c0c03cc33f62
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Install default panel mode for connector panel_mode property
so that the panel mode can be changed to default mode accordingly
when SDM is restarted.
Change-Id: I3229a1b8e60da9030d6e20112f6b1f3071b5f988
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
Currently, driver enforces the allocated WB output buffer to be 256 bits
aligned in memory in order to optimize DDR access and meet maximum system
bandwidth requirements.
Since there are no functional failures with using a 256 bits unaligned
buffer, this change removes this unnecessary check.
Change-Id: I23476e8a28e970f2e1853bbcc0c1d1042d9fdfe2
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
msm-ext-display module is moved out of the kernel to display
driver after waipio release. This change will import these
msm-ext-display symbols only for a non-waipio variant.
Change-Id: I3cb30f666120e29c13405b98c98cc540198fa651
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Set a flag to avoid multiple reading of sde_dbg info, that
reduces devcoredump reading time.
Change-Id: I83f77dea35bb818d51b0982124a54ffeef7db8af
Signed-off-by: Bruce Hoo <quic_bingchua@quicinc.com>
Enable trusted vm flag for kalama target
Change-Id: I2f2c0a838914d5fccf6642690c082c592e04e38d
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
SID registers and offsets are changed in display
MDSS 9.0.0. Changes are made to program these new registers.
Also, added new revision check for backward
compatibility.
Change-Id: I4e1ea374f38c95a4d1019c2596418bb6bb7c5347
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
This change adds the programming of the master interface
register for single interface configurations.
Setting this register is required by hw-fencing feature
to distinguish primary interfaces vs wb.
Change-Id: I84936ebd6a9f2d67cf98c19a51ce3a132c648a2d
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Because of changes to ref clock frequency, few of the pll
reg values are different for kalama compared to palima.
This change differentiates between these two 4nm versions,
based on pll revision and also introduces a pll reg table
to differentiate the values.
Change-Id: I016330ded10ab334012daa8cc288a8cd5c039f58
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
This change avoids null pointer dereference in different APIs.
Change-Id: I01eba9d64fa4ba2fd81f7f39f586867e22d66771
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
Refactor the function 'dsi_display_get_modes' to
reduce its complexity.
Change-Id: I1a8ecaa780e5070bac7fa40404677c0a8a5d7cd8
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Mitigate errors to debug logs on non-parsed regulator look ups. Callers
can make use of the return value to handle failures.
Change-Id: Ib0ed869e92104ac7e859484b247ac99bf332fa5c
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
MDSS 9.0.0 added support for logging MDP_VSYNC timestamp. Use it for
video-mode panels and rely on PANEL_VSYNC timestamp for cmd-mode panels
as it relies on external panel TE.
Change-Id: I09b25d893075bee7cb2da98d4c4b4e54eb09bd6e
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
With MDSS 9.0.0, s/w relies on the ctl-done-irq which signifies the
frame done for the ctl path. Avoid unnecessary waits during
tx-done/commit-done on the individual physical encoders when ctl-done
feature is enabled.
Change-Id: Ie5e8b08c47a4778dfa03a87dbbae8daf6a738e6a
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Fix the Watchdog timer load value calculation with jitter feature.
Change the long term jitter value check to have jitter < 10.
Change-Id: If834e16d3b8fad5009642e479f529fa5b7cf2d17
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
DP PLL driver is the clock provider for link_clk and pixel_clk source
clocks. Once the PLL is configured, the clock rates for these output
clocks must be explicitly set using the clk_set_rate() API so that
the clock framework can correctly compute any MND values required
to satisfy the requested rate at the branch clocks that source from
the PLL output clocks.
Change-Id: I14f8f58333ac5ba3f547d12a123cb5e5f05c6005
Signed-off-by: Aravind Venkateswaran <quic_aravindh@quicinc.com>
