Force callers to say if they are using 36 bit address patching or not.
CRs-fixed: 3121782
Change-Id: I4dee25e3f73104a1be043fe18a295cd4f8447821
Signed-off-by: Karthik Jayakumar <quic_kjayakum@quicinc.com>
Print out WM information on CCIF violation.
CRs-Fixed: 3121755
Change-Id: I0fffd8cf4bc7af660f120ba1df8917cd95af64b4
Signed-off-by: Anand Ravi <quic_ananravi@quicinc.com>
Corrects the variable debug print statements for expanded memory case
in IFE.
CRs-Fixed: 3120109
Change-Id: I08e2849db21459ebaecec68a7340d8d103562743
Signed-off-by: Karthik Jayakumar <quic_kjayakum@quicinc.com>
Due to hw limitation, if the required RDI buffer output is
Plain16_10/12/14, BUS cannot conver CSID unpacked MSB data
into LSB aligned while writing the buffers. So keep CSID out
as unpacked LSB data if the final RDI output buffer format
is Plain16_10/12/14. This will have limitation in using RDI
data going into LCR/PDAF.
CRs-Fixed: 3118104
Change-Id: I9193530ec549b4658a058ae71eed4f31653bd88e
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
Currently lane specific general register programming is structured
with lane index basis. This is not required as general register
needs to program without any condition. This change updates structure
of this programming register. Also, array size calculation is replace
with more intutive way rather to manually enter the size everytime.
CRs-Fixed: 3117726
Change-Id: I5e57f37bf2025b37f23c10b835fd31ddfe986cee
Signed-off-by: Jigarkumar Zala <quic_jzala@quicinc.com>
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
To avoid concurrent access to the device timers while
stopping them, keep the stop call protected with hw
mutex.
CRs-Fixed: 3080397
Change-Id: If0a5226536e3a3c14738811965511225d1a96f08
Signed-off-by: Tejas Prajapati <quic_tpraja@quicinc.com>
Extension of Let's do a reset (LDAR) for ICP to include more info.
CRs-Fixed: 3105929
Change-Id: I5fee181d009a8d69e8d3e673a552b289f72fb4aa
Signed-off-by: Joshua Florez <quic_jflorez@quicinc.com>
camera-kernel:
48c1c34 Merge "msm: camera: csiphy: Add lane enable register capability" into camera-kernel.lnx.dev
f354ed9 Merge "msm: camera: isp: Keep the data in MSB while unpacking at CSID" into camera-kernel.lnx.dev
Change-Id: If82b6a657c246dfc1872ef65acc17e939da4ec32
Signed-off-by: Savita Patted <quic_spatted@quicinc.com>
BUS, SFE pipeline(xCFA), PDAF/RDI-LCR pipeline expects the
incoming valid data to be in MSB. So, if RDI data is unpacked
to PLAIN_16 at CSID out, keep the valid data in MSB.
For final out formats PLAIN16_10/12/14/16 formats, unpack
data at CSID and keep in MSB and use wm pack with LSB write,
as LCR/PDAF can be enabled with these final out formats and
expects data in MSB.
CRs-Fixed: 3118104
Change-Id: Idb64d809ea006192eb29bb9bb57c5c12a6e8b136
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
Add and handle lane enable register offset programming independent
than common control register array.
CRs-Fixed: 3117726
Change-Id: I7a9cfe41cb425143bf2be6c48de47dfb5e117aae
Signed-off-by: Jigarkumar Zala <quic_jzala@quicinc.com>
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
To configure CP mask correct version check needs to be
used against CPAS hw version. Currently csiphy driver
is checking platform version to make the decision.
This change update this check with CPAS hw version check.
CRs-Fixed: 3048249
Change-Id: Id023f5cc0252b47c274dfed9d93e7f49a3d0ab49
Signed-off-by: Jigarkumar Zala <quic_jzala@quicinc.com>
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
After flushed, KMD reports ERR including isp, actuator, sensor, flash.
However many CRs don't have fatal KMD error log, but participant is KMD.
Remove the non-fatal KMD error log.
CRs-Fixed: 3095401
Change-Id: I0e5e370c0c4d1daceb72d9eed8d0c45baad5179e
Signed-off-by: Wang Kan <quic_wkan@quicinc.com>
camera-kernel:
c8e56da Merge "msm: camera: cdm: Fix the CDM Reg dump" into camera-kernel.lnx.dev
e63fee2 Merge "msm: camera: isp: Add support for the new error codes" into camera-kernel.lnx.dev
Change-Id: I5a62e828fbaa686af2b2dd84f1ad879cf6562b5e
Signed-off-by: Savita Patted <quic_spatted@quicinc.com>
Add support for more error codes in the kernel code to
report more errors to user.
CRs-Fixed: 3112574
Change-Id: I6eef2bd73d5ff7cac9d0ed95682c76c4438cfa47
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
We acquire RDI0 by default for SFE cases without RDI out ports.
We need to skip RDI0 resource acquire if RDI0 is already acquired
previously.
CRs-Fixed: 3092119
Change-Id: Icb62b07f03b1ac14560ca152e6fca479a4acb1a4
Signed-off-by: Chandan Kumar Jha <quic_cjha@quicinc.com>
Updates board list of supported msm-mmrm boards to include kalama.
CRs-Fixed: 2980570
Change-Id: I182ef8b56b67c24d1ad9c4b23f475782f93e8aed
Signed-off-by: Karthik Jayakumar <quic_kjayakum@quicinc.com>
Combine the num_exp for sHDR EPCR case, and we can
override the mode switch related parameters only
when the mup is enabled in new req.
CRs-Fixed: 3106141
Change-Id: I1bd0b38402962ca598f2e5c6bd528a0af2adc55f
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
Extension of Lets do a reset (LDAR) to include more information
in dump with more dump output enhancements.
CRs-Fixed: 3068971
Change-Id: I6b61bcf546e32c096e45c511faf64514ff391e62
Signed-off-by: Joshua Florez <quic_jflorez@quicinc.com>
Fix few incorrect log and add ctx id for
irq handling log.
CRs-Fixed: 3101894
Change-Id: Ibd2783124ed6354a379b9804e6e6bc01f2ab6fb3
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
Add data struct for reporting v4l2 event on page
fault. Upon receiving the event, userspace is
expected to abort, and all kernel drivers are shut
down. when Titan power on the next session, CAMSS
will undergo async reset.
CRs-Fixed: 3109439
Change-Id: I518148baa2414fd072b874200a408589332f95ec
Signed-off-by: sokchetra eung <quic_eung@quicinc.com>
Kailua tpg has some extra register for ir/xcfa/shdr overlapped.
These register data support is added as part of this change.
CRs-Fixed: 3086082
Change-Id: If044b336a87de931f6d512c52895e65c85d10863
Signed-off-by: Rishab Garg <quic_rishabg@quicinc.com>
Add interleaving format to support 2PD for tpg0.
CRs-Fixed: 3100297
Change-Id: Ic59c4cec0990faa3d70f45aa34baebaa33e08b2b
Signed-off-by: Rishab Garg <quic_rishabg@quicinc.com>
For SFE 780, Input to SFE from CSID for single xcfa use cases
is RDI0.
This commit changes the acquire logic to acquire RDI0
in case of SFE context for single ISP/SFE use cases and IPP
for dual ife cases.
CRs-Fixed: 3092119
Change-Id: I7e7ba0438435c6fe7a8b0d22f7c08b7ce4da1819
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
IRQ line verification can now be triggerred from JPEG HW manager by
writing to a debugfs file as follows:
echo 1 > /d/camera/jpeg/test_irq_line
IRQ line verification can also be done at probe if
CONFIG_CAM_TEST_IRQ_LINE_AT_PROBE is set to true during compilation.
Both debugfs and probe-time verifications are only active if
CONFIG_CAM_TEST_IRQ_LINE is set to true during compilation.
CRs-Fixed: 3071027
Change-Id: Ib24022a12e3aa3ac529c7bc925fd4df1f2a96310
Signed-off-by: Anand Ravi <quic_ananravi@quicinc.com>
IRQ line verification can now be triggerred from ICP HW manager by
writing to a debugfs file as follows:
echo 1 > /d/camera/icp/test_irq_line
IRQ line verification can also be done at probe if
CONFIG_CAM_TEST_IRQ_LINE_AT_PROBE is set to true during compilation.
Both debugfs and probe-time verifications are only active if
CONFIG_CAM_TEST_IRQ_LINE is set to true during compilation.
CRs-Fixed: 3071027
Change-Id: I386548d1ed817674be8322c8be792e2c57f9d166
Signed-off-by: Anand Ravi <quic_ananravi@quicinc.com>
Sometimes, all the buf dones of bubble req have been
received, but they are deferred buf done. If we handle
the deferred buf done before moving the req to active
list, the req will be moved to pending list first during
processing the buf done of bubble req, then moved to
active req list in the processing of epoch_in_applied.
This change moves the bubble req to active list first,
then handle the deferred buffer done.
CRs-Fixed: 3096361
Change-Id: I1e9b1ba5a46509b1c08ec92bbca0c2d7fbde679c
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
