Supported dynamic HW mode switches:
DBS (full band 5G and 2G) <-> DBS_SBS (low band 5G, high band 5G and 2G)
Description of the changes:
1. NOL conversion:
a. Introduce a temporary NOL list copy structure in DFS psoc obj.
b. When mode switch is triggered:
i. Stop the NOL timers and clear the data, to avoid processing NOL
expiry during mode switch.
ii. Allocate the psoc NOL copy for the target num_radios.
iii. Store the NOL data of each radio to the target pdev ID
(pdev ID after mode switch) in the psoc NOL copy,
using a unified mux/demux API.
c. After mode switch is completed:
i. Resume NOL by re-initializing the list from the temporary psoc
copy.
ii. Free the psoc copy after mode switch is complete.
iii. Note: changes are made to support pause and resume of NOL,
increasing NOL timeout by a few milliseconds.
2. PreCAC list conversion:
a. When mode switch is triggered:
i. Stop the existing preCAC timer and send ADFS abort command to FW.
b. When mode switch is completed:
i. Unify/separate the preCAC list if the target mode is DBS/DBS_SBS
respectively, using a single API.
ii. Start ADFS again.
3. Radar detection lock:
a. While detecting radar, acquire a lock to avoid handling user triggered
mode_switch during this process. Release the lock once radar
processing is completed and CSA start is triggered.
4. Radar detection/CAC completion defer during mode switch:
a. While detecting radar or CAC completion, check if mode switch is
in progress. If yes, defer the processing and wait for mode switch to
complete before handling the events.
b. Note: Precedence is Radar over CAC, i.e., if CAC processing is waiting
and radar is received, CAC completion is no longer handled.
CRs-Fixed: 2580403
Change-Id: I506f3b569bad2e351c6f336e50f203cf5fa8b223
Add initial set of coex files, implement the basic functions.
Coex component is used to process coex related configurations.
CRs-Fixed: 2565088
Change-Id: I8b9600809691b808f97c621cb329a6ab9941814c
CFR config is passed on to FW through WMI
CFR feature code is moved into feature specific WMI file.
Change-Id: I00b57ea2ef4ec5520eb565910ac2c0a6478170e3
CRs-Fixed: 2582846
In regulatory non-offloads feature, send conformance_test_limit_2G,
conformance_test_limit_5G, reg_domain, reg_domain_2G and reg_domain_5G
information to firmware using WMI_PDEV_SET_REGDOMAIN_CMDID.
If all these attributes are not populated then CTL power limit is
not applied by the firmware.
Change-Id: I1523ab447aec64ec0af42da32318136f90fd17ca
CRs-Fixed: 2518246
Depending on the requirement, a bigger size or a smaller size for
the frequency variable can be chosen. The advantages of each size
are described below:
Advantage of a bigger size:
When two technologies (e.g. 802.11AX and 802.11AD) are controlled
by the same driver software, the frequency range may be very large
and a bigger size (e.g. 32bit integer) is more appropriate.
Advantage of a smaller size:
When the frequency range is not very large, a smaller size
(e.g. 16bit integer) can be used. It saves a large amount of space
especially when many large arrays containing elements of this type/size
are defined in the driver.
Also, change the size of the IEEE channel variables to unsigned
8-bit integer.
Change-Id: I6349c0665bf0a7329627427913f9eebba2821043
CRs-Fixed: 2586177
Add code to change the vdev_mlme timers to psoc_mlme timers
and also change code to send vdev_delete to FW while physical
destruction of vdev obj.
Change-Id: Ie041182155c75d0cc3825dc97b26abc6be38d76c
CRs-Fixed: 2563931
Wakelock is system level lock not required to be taken
for every vdev, Hence move the wakelock to the psoc
hierarchy.
Change-Id: I525baf5f4b5dcadb493d84900dbd0a2e7c6407f6
CRs-Fixed: 2563406
Move the vdev response timer from the vdev object manager structure
to the psoc mlme structure.
Change-Id: Ieb87ac6549aa23e0beb61441fea459d3db78c2f3
CRs-Fixed: 2563410
All gen III chipsets use Direct-DMA mechanism to copy Spectral reports to
the Host for further processing. This mechanism involves ring and buffer
management in the Host, FW, and uCode, where improper/incomplete DMA and
improper tail update issues are seen. DBR framework provides support to
debug such issues. Add Spectral control path support to facilitate the
configuration of these debug options.
CRs-Fixed: 2478596 2478595
Change-Id: I094616c4137145389b6984ccab933e5ebd0aa1ab
To enhance visibility of 6GHz AP, 6G only AP shall send
Fils Discovery frame periodically in one beacon interval.
Change-Id: I51487380fca10418d2260dc2612e2adcf6cbb93b
CRs-Fixed: 2562434
Improper/incomplete DMA by the target affects the functionality of modules
that are using DBR framework. Add debug infrastructure to poison DBR
buffers with a given poison value before handing buffers over to
the target. Buffer owner modules can explicitly check for the poison
value in order to detect the improper DMA.
All modules that use DBR framework can use this debug infrastructure.
Change-Id: Ib3923c13202990e0f1198645b680c44a20736167
CRs-Fixed: 2466518
Add debug infrastructure to track the movement of head and tail pointers
of the DBR ring along with the time at which each buffer is received and
replenished. All modules that use DBR framework can use this
infrastructure. Issues that are specific to tail index movement from
the target can be identified with this debug infrastructure.
CRs-Fixed: 2439460
Change-Id: I6b486a73cf6a3174dfa297f8fb370fd298b46b67
Add regulatory APIs reg_get_unii_5g_bitmap and ucfg_reg_get_unii_5g_bitmap
to retrieve the value of "unii_5g_bitmap" stored in regulatory pdev
private object.
CRs-Fixed: 2574642
Change-Id: Iffb004b7fc9d9fbcf1972eb6f527529024e49c70
The 5G cellular RF band and wifi frequency band of UNII-1
(IEEE channels 36, 40, 44, 48) and UNII-2A band (52, 56,
60, 64) can coexist.
UNII-1 and UNII-2A are represented by bits 0x1 and 0x2 respectively in
this implementation. The user space command should set the bits by
applying the following algorithm:
1) To disable only the UNII-1 band channels, set the value as 0x1.
2) To disable only the UNII-2A band channels, set the value as 0x2.
3) To disable both the UNII-1 and UNII-2A band channels, set the
value as 0x3.
4) To restore both the UNII-1 and UNII-2A band channels, set the
value as 0x0.
Change-Id: I8ff747e53b079ee9e0dc762980aee0eea32b23a5
CRs-Fixed: 2571546
Add API to know whether 6ghz is supported. Also add API to know
whether an operating class is 6ghz operating class.
Change-Id: I75747502c0033e31d119e58a2254b220646bba10
CRs-Fixed: 2556998
As FW requires, send WMI_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMDID when there
is no beaconing session in DFS channel for FW which supports dfs offload.
Change-Id: I73b86328be6eb132de70bd10406495fbaefcab67
CRs-Fixed: 2554083
To avoid "channel number" collision that was introduced after 6Ghz band was
added to the driver, add frequency based APIs to Global UMAC dfs
dispatcher.
CRS-Fixed: 2526372
Change-Id: Ice72aae699f609f9dadd0717852fa848cb392629
The decision to do CAC when a vap is coming up should be taken based on
the previous channel and current channel. Introduce previous channel
in DFS structure and update it when the current channel is updated.
Use the previous channel and current channel in DFS structure to
decide whether the CAC should be done or not when the vap is coming
up.
Change-Id: Ia359025d5029713c32696dacee5b89618a1c9707
CRs-Fixed: 2538653
Based on the ini "ignore_fw_reg_offload_ind" ignore regulatory
offload indicatin from fw.
Change-Id: Ia95b5bdda6ee1fcc2b07f28f997a7c80afcbc32b
CRs-Fixed: 2533001
Enable configurable dfs_pri_multiplier. The ETSI typ2 type3 radar
detection ratio is lower than expected(>80%) while channel loading is
high(>30%). The host improvement for this are:
1. Add configurable dfs_pri_multiplier, controlled by
DFS_PRI_MULTIPLIER. Default value 2, min 1, max 10.
2. Lower adrastea ETSI type 2/3/4 radar filter rssi_threshold,
controlled by DFS_OVERRIDE_RF_THRESHOLD, dfs log shows that
QCS405 target report RSSI range [18, 45] while radar power
is 3 dbm. By using default rssi_threshold 24 will reject
many radar pulses, which leads to low detection ratio.
3. Calculate deltapri for each searchpri based on dfs_pri_multiplier
in dfs_count_the_other_delay_elements(), check deltapri
between [1, dfs_pri_multiplier] * refpri and searchpri, if
the primargin is desired, mark it as matched pulse.
4. Pick lowpri as refpri for the radar filter with
rf_ignore_pri_window equals to 0 while DFS_PRI_MULTIPLIER is
enabled. Observed original findref logic has some problems
which selects refpri is bigger than lowpri, which leads to
the lowpri pulses pri_match are set to 0, and in this case,
radar was not detected. Example for the issue, assume
rf->rf_pulseid 34 (ETSI type 2) has 7 pulses with pri:
1489, 2978, 2978, 2978, 1489, 2978, 1489 us in this case,
highscore is 4 (2978), scoreindex is 5, refpri is 2978, which
leads to: index 0, 4, 6 pulses with pri_match 0 in
dfs_count_the_other_delay_elements(). The fix is to select
lowpri as refpri(1489 in this case).
Change-Id: I1f3ca3298c9ab1f1e2651ad6b4a0a4810f83f8a1
CRs-Fixed: 2531811
Agile DFS support depends on the Firmware's aDFS support. This
information is propagated to the HOST in the WMI ready event as a flag.
This flag was not used by HOST before enabling agile DFS which resulted
in preCAC being enabled for the FW that does not support them.
Also, for certain chainmask configurations, aDFS should be enabled
only if the current pdev is operating in non 160 BW.
Introduce two new flags in the DFS object:
1. dfs_fw_adfs_support_160
2. dfs_fw_adfs_support_non_160
which specify FW support for ADFS for pdevs in 160 BW and non 160 BW
respectively. Make appropriate changes in is_agile_precac_enabled
check that includes fw support for the current operating bandwidth.
Also rename "dfs_agile_precac_enable" to "dfs_agile_precac_ucfg" and
"dfs_precac_enable" to dfs_legacy_precac_ucfg" in the dfs structure
to properly indicate what those booleans represent.
Change-Id: I202ead8ef109c707bfbda488064ecaa72a3f737f
CRs-Fixed: 2521654
Currently as part of tdls enable link, If the peer is buff
capable or tdls uapsd is enabled in INI. UAPSD is enabled in
FW. Avoid sending this command to FW as it effects the behavior
with AP.
Change-Id: Idc023cb9de3ab63e7643815d473fe0efa98069b9
CRs-Fixed: 2528324
It required to support multiple srng per module in direct buffer rx
component.So extend the array "dbr_mod_param" in dbr pdev object and
let it to support two more srngs per module.
Change-Id: Ia2c649dacc3787cdc13b06f0b22c1c175fb451cc
CRs-Fixed: 2523365
Add helper API to get the center frequency of secondary 80 MHz
segment. Make this API available to Spectral target if layer
via rxops.
CRs-Fixed: 2523690
Change-Id: If1cad90d9b27d1461e802b921aecda07031b1e0b
Vdev decap/encap type has been set when vdev create, don't need
set again when vdev up.
Vdev mlme mgmt.generic.rx_decap_type isn't initialized, can't be
used to set vdev decap type.
Add tgt_vdev_mgr_set_tx_rx_decap_type to set vdev tx/rx cap/decap
type by wlan_util_vdev_mlme_set_param.
Change-Id: If487a890eafd0e4e5e6cda31c22d459e342770de
CRs-Fixed: 2516997
Add an attribute which describes the error code
in the response to set config, start scan and stop
scan.
CRs-Fixed: 2500481
Change-Id: I491cd6e061d2d08ceb4d9af2a7de5223e229c280
Currently a single API(dfs_get_precac_enable) is used to get
dfs_precac_enable and dfs_agile_precac_enable. This API is
wrongly returning value for dfs_precac_enable since agile
capability is set even for Cascade.
Separate out the GET APIs for getting dfs_precac_enable and
dfs_agile_precac_enable so that getting these flags becomes
independent of each other.
Change-Id: I08b0cbcd29c320a345865e3e9456ce3e809e26a6
CRs-fixed: 2501266
WIN and MCL both uses common targer_if code for vdev manager.
So legacy code and "CMN_VDEV_MGR_TGT_IF_ENABLE" macro is removed.
Change-Id: I2984ae44f3a7cfa01b8f1455353d09deb4db5759
CRs-Fixed: 2503804
Provide Global function pointers for accessing DFS/REG APIs that
1. Build channel list as per the configured HW Mode.
2. Reinitialize DFS timers after mode switch.
3. Reset ADFS Config.
CRs-Fixed: 2481535
Change-Id: Ied4d13b0c3ce39e696f273a7ac1f51962671c734
Provide Global function pointers for accessing DFS APIs that
1) allow or prevent the HW pulses. HW pulses are to be prevented
to detect the synthetic pulses.
2) query whether the HW pulses are allowed or not.
Change-Id: Id1e90ba6682afe747774b46da78f7ae6b56c94e6
CRs-Fixed: 2484584
For multi-radio SoCs, wmi handle is maintained per pdev to map to
separate copy engine used for sending WMI commands to taget. Add support
to send wifi position related WMI to send it per pdev.
Change-Id: I300be2bbfd77cb9390fef37b5b02a002284976e0
CRs-Fixed: 2495277
Send proper minimum and maximum agile preCAC timeout values to the target
as part of starting agile DFS detector. Add a common agile preCAC
parameter structure with the timeout values, channel and width fields
which are to be sent as part of configuring agile detector.
Change-Id: If5f5b179aa12a6c549cb9a4402aa10e957129d78
CRs-Fixed: 2482929
Currently vdev response start timer logic is in
target_if layer and stop timer logic is in tgt
layer which is asymmetry.
So, move stop timer logic from tgt layer to
target_if layer for vdev start, stop and delete.
Change-Id: Ia06e2e6d90cf9c4366d654e016e2eeab8c2a0719
CRs-Fixed: 2442199
Add lmac support for vdev delete all
peer request which will replace individual peer
delete for peers under a vdev during vdev down.
Change-Id: I98b5228c17b08eedd50b82372efe1b249cef2699
CRs-Fixed: 2477650
Currently, wakelock apis are in wma. Create vdev resp wakelock apis
in target_if. Plan is to remove it latter from wma.
Change-Id: Ib410ee2404751544db2f291b466ff0d6ff248e8f
CRs-Fixed: 2441245
Add regulatory rx_ops for setting DFS channels availability to be
called from Offload layer.
Change-Id: I15cec0f119baf5668052618dc3a2552470d1f14f
CRs-Fixed: 2384202
Add code to enable sending target_if vdev response to host,
if FW fails to send response within expiry time.
Move timer free functionality to vdev destroy path so as
to make the system not to go into deadlock
Change-Id: I72bdecf2502a755ffc09414f8b72d230bf9c559f
Crs-Fixed: 2449238
CFR requires to configure the number of DBRs that can be packed
in a single DBR event. Currently, this is fixed value.
Make this configurable at the time of registration.
CRs-Fixed: 2415489
Change-Id: Ifcd606641f986a5345f8ccb361c3f45db07fdc37
Add change to use wmi_service_enabled for
wmi_service_sync_delete_cmds instead of using
chipset specific name in target_if
Change QDG_BUG to QDF_DEBUG_PANIC in target_if
vdev response expiry handler.
Change-Id: Ie0f3de2a043198e5aaf5a11add3b8e13b6a47812
CRs-Fixed: 2407877
CFR needs to correlate data received from direct dma ring and WMI event
for tx completion. These two events can come in any order. To facilitate
correlation CFR module has to hold on to the buffer until both events
are received and then replenish buffer back to direct dma ring. To
facilitate this requirement direct rx buf module is modified to change
callback return to bool to indicate whether buffer can be replenished
immediatley or not. Also add API to indiciate buffer release/replenish
later.
Change-Id: I7f0bd7f41ee9362374a5aeb6f506d3f101ec4536
CRs-Fixed: 2403399
If user configures DFS channel in 160MHz mode,
1. change mode to 80MHz and do PreCAC on primary and
secondary channels of 160MHz.
2. Use intermediate channel to operate.
3. Once PreCAC done on the both primary and secondary channels and is clear
then change mode back to 160MHz.
4. Change the channel from intermediate to configured DFS channel.
Use Broadcast and Unicast OMN frame to notify mode change.
Change-Id: I1f2db0f38b42fce2f407988041edfea9c49c58e1
CRs-fixed: 2395431
Enhance target_if/mlme/vdev_mgr by addressing
review comments and update response handling
APIs to handler timers and response bit maps
as expected
Change-Id: I8a5bf3f2931f0c36a367dfebfc898ed2621f3516
CRs-Fixed: 2397184
