During drm_bridge_mode_fixup, we deny a simultaneous crtc state
change and seamless variable refresh. Incorrect translation logic
between drm_mode and dsi_mode made it such that whenever the dsi
bit clock is not the default value, any drm commit would be marked
with the variable refresh flag, denying all suspends. This change
fixes the suspending issue.
Change-Id: If3c1f603af3e2917f82be6487bee1084a6e1b605
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
Extension bits of test point selection is needed when test
point value exceeds three bits, not based on blcok id value.
This change fixes debug bus test point selection when
value is more than 3 bits and extension bits are required.
Change-Id: I37688b2c6e476b1271daad0bbddb5896edc530d1
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
The driver currently inserts a failsafe mode when EDID read fails
for SST. But for cases where the edid read succeeds but all the
modes are getting filtered out because of resource availability,
the driver does not add the failsafe mode. But the usermode
expects the failsafe mode to be always present in the mode list
as per DP specification. Also, the driver currently does not
add the failsafe mode, if the edid read fails on an MST monitor.
This change covers all these missing cases and makes sure the
failsafe mode is always in the connector's mode list if it is
in connected state.
Change-Id: I92eeaa00ad7b26a18b3689aa1c2ada4244aba3bc
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Allocate DSC inversely for non built-in displays to avoid Quad DSC
can't be contiguous reserved as the below scenario.
Use case: Primary display with 2 DSC, and DP display can support 8K@60
with 4 DSC and 4k@60 with 2 DSC.
--> when both display are in powered off, all DSC blocks are free.
--> enable DP display with 4k@60.
DSC 0/1 is allocated by DP display
--> enable primary display.
DSC 2/3 is allocated by primary display.
--> switch DP display to 8K@60
DSC 0/1 + DSC 4/5 are allocated by DP display.
But the DSC must be contiguous allocated for Quad pipe.
Change-Id: I465c115bb7ec775483dc6a984306a9aa51750b14
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
Demura backlight value will be updated based on the backlight event
in the driver. Make HFC gains programmable based on backlight value.
Signed-off-by: Mitika Dodiya <quic_mdodiya@quicinc.com>
Change-Id: I74e9aa2c274eedb473095c5eafef194d6a6f1d94
Currently, ctrl lock is taken while waiting for CMD DMA done even in
case of ASYNC command transfer, which doesn't allow any other operation
on the controller until the command transfer is done. Avoid this by not
taking ctrl lock while waiting for CMD DMA done.
Change-Id: I91f2638fa02f48ec4c7a41c750daa46b52c5e2f2
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
When calculating the number of DSC slices based on the source
and sink capabilities, the driver is using an incorrect check
for max slice width which results in increasing the num of
slices if the width is an exact multiple of 2560.
Change-Id: Ia854c4a2d436144165fb52beb04b5e0d1678d0f6
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
To optimize evt log entries, spinlock is been removed and
used atomic operator for curr variable, due to which there
is mismatch of count values between curr and last variable during
xlog dump in kernel. So change the last variable to atomic to
avoid race condition between entries of evt logs.
Change-Id: Idf3e2b982261d77fec97985af1e8bf740a6f6197
Signed-off-by: Ryan McCann <quic_rmccann@quicinc.com>
Update the string formatting of debugbus dump header
to support existing scripts for debugbus parsing.
Change-Id: Ie0b4fdcb73e131ea5893a3dbc6aad969735d137d
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
During HPD High, the driver sets the CONNECTED state and then performs
a sequence of initialization operations. If any of them fails, it should
properly unwind the executed operations to restore the driver to its
initial state. This change adds error handling paths in the hpd high
handler to do just that.
Change-Id: I66a77ff73b7c11d0a59d80b8df3c4ea49a4ed3a6
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
During qsync frequency step down, it is possible for the changing
frame window to lead to frame buffers being transferred when it
is unsafe to update. Pineapple r2 hardware supports using the
panel's TE level, instead of the start window, to trigger the
frame transfer.
This change enables using TE level during QSYNC or AVR, if the
hardware supports it.
Change-Id: Ie675edaaeb80921c639905395b709f4c67134fc7
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Reduce the MDSS IRQ processing latency by skipping the status
register read/write of the interrupts which are not enabled.
Change-Id: Id86057ad3ab043ad76d4d4b44a373eff3b55da4d
Signed-off-by: Shirisha Kollapuram <quic_kshirish@quicinc.com>
Add dsiclk_sel support for both DPHY and CPHY, update pclk_div
calculation w.r.t dsiclk_sel as per HPG.
Change-Id: I573addd62c77d1c9f089b7aadf386cd2e579f442
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
Rename dsi_clk mux as dsiclk_sel to match the naming convention
with HPG.
Change-Id: I50671a78fccdd10d74d43fdf8ef4ede0c55fd09b
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
Support 8bit and 10bit bpp switch for display.
Change-Id: Ia5fcb330df95618596377773d0598be2b5609de1
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
In case of DATABUS_WIDEN, follow the HPG to calculate bitclk,
byteclk and pclk. Configure the DST_FORMAT and the clock
dividers in DSI PHY and DISP_CC w.r.t. the bpp before
compression.
Change-Id: I526eab5bc88b8d667b8b1a0d257b2f147998286a
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
During MST display enablement, the time slots for the display are
calculated during mst atomic check, which is then used in the
enable path. But if for some reason the payload wasn't allocated
successfully, then the enable path will have the time slots set to
0 which causes a send video timeout and also the missing payload
could result in null pointer dereferencing in step2 of mst payload
addition.
This change checks for this situation during pre-enable and returns
an error so the enable does not continue ahead.
Change-Id: If139707537b7a6dba169841ac82841851b4c09cb
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Previously we were updating internal layer mixer allocation
bookkeeping during every mode validation regardless of whether
the mixers were already designated in use, resulting in double
counting of in-use layer mixers.
This change prevents modification of these values if the given
connector's mode has already been previously validated so valid
modes can be returned properly.
Change-Id: Iea5dccfbc4087cc76f186101d38b605792326b16
Signed-off-by: Andrew Bartfeld <quic_abartfel@quicinc.com>
Disable CWB in quad pipe for quad LM CWB not supported
to avoid out of bound access.
Change-Id: I7e64cf132489401f91621ccde31cba68c8076d28
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Change increases cmd dma timeout to 1200 milliseconds from 200 milliseconds.
There are video mode panels which can support one frame per second, if pixel
data transfer is active, then our command transfer timeout should be atleast
1000 msec.
Change-Id: I3d650d787fa6557ce474aca977906b99af1f1cbc
Signed-off-by: Rohith Iyer <quic_rohiiyer@quicinc.com>
CPU qos_mask populated from devicetree can have defective cpu cores
included. This change identifies and replaces the defective cores
in the qos mask with the next possible working cpu cores.
Change-Id: Ie6bad11ff36f8e2486ef568b67b3fe024f9786c7
Signed-off-by: Andhavarapu Karthik <quic_kartkart@quicinc.com>
