Fence error handling for wb and cwb retire fence.
Signal the retire fence for the fence error frame.
Change-Id: I0f73195c50edab4b8aefb58cea342214be87584c
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Reset lut dma when fence error is seen to reset the already
submitted queue.
Change-Id: Iba9ab33a2e80bdaba6b1d4ccff086e3a46f8374d
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Add framework for display submodules like PP, DSI, DP to register
for fence error and call the client callback funtion when fence
error occurs.
Change-Id: I70cc6b01907177e6c4238c4398fe2c085a000322
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Sw fence error handling addresses following:
a. out of order handling
- For cmd panel, signal the release fence and retire fence once
sw fence error detected.
- For vid panel, signal the fence error frame release fence and
retire fence once sw fence error detected, hold the release
fence of last good frame till next good frame.
b. avoid BW decrease vote
c. lut dma reset
d. cancel kickoff
Change-Id: Ic496c532a26d80e0ef0074624ef6ace01c4ab2f0
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Handle out of order dma fence signalling and propagation of fence
error. Out of order fence signaling is required only in Video mode.
For example, in case of N, N+1, N+2 frames where N, N+2 are good
frames and N+1 is frame with fence error. The release fence signal
sequence in video mode would be N+1, N, N+2.
Change-Id: I8b6f88cfeee945e28571b765f24ffea22fad23b8
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Register callback function to hw fence driver and implement the
callback funtion.
As part of fence error handling, address out of ordering of HW
fences, SW override for release fence signal and handle BW voting
in both cmd and video mode.
Change-Id: I22902762b4cc09a5f5a20cf0dd01fc336a0f0cb4
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Add a new property CRTC_PROP_HANDLE_FENCE_ERROR for userspace
to enable or disable fence error handling.
Change-Id: I72370f405c5299c603b0d673720c28a68c00807a
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
While clearing all blend stages, avoid writing blend config
registers for invalid dummy layer mixers introduced for dcwb.
These dummy mixers are SW only representation, these mixers
do not have respective blend config register space defined in HW.
Currently blend stage clear logic clears other undefined and
some valid registers like CTL_x_SW_RESET_OVERRIDE which is not
intended. This change limits accessing blend config registers
based on actual HW layer mixer count by ignoring dummy mixers.
Change-Id: I3a61fb6d5522b041fd6f10305b84dae449b4f2c7
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
In Current SDE driver, perf update check avoids bw update
in RSC state transitioning from CLOCK to SOLVER and updating
cached cur_perf bw values with out actual update to bus causes
bw update miss until usecase change trigger a new bw values
from client.
Below is the sequence of events in issue scenario.
-> wakeup frame from suspend, start with max bw voting and
framedone successful
-> RSC state updates to CLOCK state because of delay in next
incoming frame
-> Next frame perf update with paramschange, bw update is
skipped as new bw < cur bw and RSC is in CLOCK state
-> RSC updates SOLVER state after above step and commit is flushed
-> Bw update after frame is also avoided because RSC is in SOLVER
but cur_perf is updated with new bw value.
-> from next frame if bw is same as perevious frame, voting is skipped.
until change in bw values, vote of max bw in first frame is left.
This change fixes updating cur_perf values only when actual
bus update is intended.
Change-Id: If3ea4f178b94e9e59cd8ca563fa3510dffcc15a5
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
In non-qsync panels when min FPS is not published in DT,
the default min fps is set to 10 FPS. This change handles mode
switch cases, when panel FPS drops below 10 FPS by updating
min FPS to panel FPS for Expected Present Time calculations.
As part of the change, reduce 2ms from EPT to account for
scheduling delays after schedule_timeout.
Change-Id: Idc206f39adfb3517b4ea2cfa303fe53182a8e63e
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Propagate error in case the number of active displays is greater
than 1, in dual display scenario to fail the validate.
Change-Id: I04250af8d7a6b0c290132abbaed2ed8e5e311a4f
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
From MSSS 10.x, the src_en bits needs to be set appropriately for
vid/cmd mode for getting the vsync timestamp. Program it based
on the new feature flag SDE_INTF_VSYNC_TS_SRC_EN.
Change-Id: Ia9c59d66afb436f082c7ebe6bf28e3953fde27a5
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
With DP plug-ins, it is possible for the connector fill modes API
to be called to update available modes on the connector and at the
same time have the commit thread calculate the max mode width
on the available modes. As a result, it is possible to access
pruned modes from the modelist.
This change moves the calculation into the fill modes call-flow,
so that the max mode width is determined once, and stored to be
used during virt enable.
Change-Id: I6c332c57e6e98ed98444a303add97d163a2031bf
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This change updates the hw-fence QOS priority level.
Change-Id: I61e832f15d060cd563986dbd7135c00fce9dd5c9
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Signed-off-by: Grace An <quic_gracan@quicinc.com>
The llcc_slice_getd/putd APIs were previously used to get/put the
slice descriptor reference, for every time the driver needed the
descriptor. However, the APIs should be used to get the reference
once, and only put after completing usage of the slice
(ie. if the slice is still active, the descriptor cannot be putd).
This change corrects the usage of the llcc_slice_getd/putd APIs by
storing the descriptor after initialization.
Change-Id: I33e6448290ff7a4d8bfa72e1e6bc8ca133283e12
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This reverts commit ae24e846e1.
Enable the feature only when user-mode support is added. With this
feature enabled in driver, it expects EPT_FPS to be set for qsync
enabled cmd-mode panels and will not honor EPT(expected present time).
With the EPT_FPS feature disabled, all panels cmd/video with/without
qsync can use EPT.
Change-Id: Ib8b1625bb1927ece3ec435e4b9a724da0555e518
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
If DSC 4hs merge is enabled and disabled on n+1 commit, possible
due to resolution switch, driver does not currently clear the
previous programming.
This change cleares dsc 4hs merge enable if it is not enabled.
Change-Id: I4024073362257b7efabcff22603bcb28a0bc4c5a
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Add a read only debugfs node to get current uidle status.
Usage:
cat /sys/kernel/debug/dri/0/debug/core_perf/uidle_status
N: indicate uidle is disabled.
Y: indicate uidle is enabled.
Change-Id: I7f28b406588c19decc4efc9012f5bac63925618a
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
Currently, only rc ram is programmed through lut dma and
rc config is programmed through ahb.
This change programs both rc config and rc ram through lut dma.
Change-Id: I50a6e87dfbadb9c4a93cebdaa1e813f5be9ba5f5
Signed-off-by: Saurabh Yadav <quic_sauyad@quicinc.com>
Expose Expected Present Time property to usermode immaterial of the
panel qsync support. EPT can be used to delay the frame with/without
qsync support.
Change-Id: If4e628dda64181995ba9ba0b008d15d3d9a9cfd4
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
For usecase with S2-only or TVM buffers, the mapping needs to be done
after the SCM call. This is required to ensure the mapping is done to
the correct SID. Previously with S2-only usecase, the map was returning
the PA which would remain the same, so there were no issues even though
the map sequence was incorrect. But this sequence will cause issues with
CSF-2.5 as it uses 2-stage with TVM, and requires the mapping to be done
after the scm-call. Fix the sequence for legacy secure-camera preview,
legacy secure-display and CSF 2.5 solution.
Change-Id: Id663d30fdbf8725f43f61e67d2d7ce72aa9f9506
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
In some vm transitions, pp work might get executed on event thread
after handoff is completed on commit thread leading to crash.
This change flushes the pp event thread queue during vm pre-release
before lending the io resources to the other vm.
Change-Id: I53b76e48bc15084aa5519409fae0e692f49e7558
Signed-off-by: Saurabh Yadav <quic_sauyad@quicinc.com>
Signed-off-by: Lakshmi Narayana Kalavala <quic_lkalaval@quicinc.com>
This change adds the check for hardware ownership before
reading the histogram statistics.
Change-Id: I0f811cef327c1dea9fb132d5fffd8da445e9d73f
Signed-off-by: Lakshmi Narayana Kalavala <quic_lkalaval@quicinc.com>
During cwb disable, encoder reset should be invoked to clean up
and release hw resources. This encoder reset should happen even
if cwb encoder TX_DONE is not successful to avoid rm rsvp leak.
Change-Id: I81353f19b69cb68d71f7d5b6477e37b6dab3ae00
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
In the case that the hw-fence feature is enabled in the display driver dt
but disabled during initialization by the display driver when hw-fence
driver dependency is disabled, the existing check to determine
if the function pointer is available is not sufficient to determine
if the feature is enabled. This change adds an additional check to ensure
we do not set the output-fences sw-override unless hw-fencing is enabled.
Change-Id: I7f5000037e7b2a142224ef9c45b383e5c701350a
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
In back to back partial update cases with CWB the CROP
registers are not reset causing WB timeout in the
following sequence-
1) Nth commit WB_roi != LM_PU_roi, WB CROP registers
are programmed.
2) N+1th commit WB_roi == LM_PU_roi, WB CROP registers
are not cleared retaining old values.
Clear the WB CROP registers in the second case to fix
the issue.
Change-Id: If09a697f48ecaf5ee08d6313be444748d048b20d
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Current implementation we apply the color properties when atomic begin
is called and mark features as dirty if crtc is not enabled.
For some of the non double buffered features in video mode we will
see a corruption. Change removes marking color properties as dirty
based on crtc on/off.
Change-Id: I4d93b14627d2bc06fcbca3ea9538a4baedb00e56
Signed-off-by: Lakshmi Narayana Kalavala <quic_lkalaval@quicinc.com>
As we are merging upstream patches, resolve conflicts of namespaces in
downstream modules.
Change-Id: Id3af0de7102ddd92e312cb3cca10db9968974bcd
Signed-off-by: Prakruthi Deepak Heragu <quic_pheragu@quicinc.com>
Signed-off-by: Raviteja Tamatam<quic_travitej@quicinc.com>
This change adds hardware programming that will update the
txq wr_ptr upon output fence firing.
Change-Id: I79ff0ea5fb2b7f73a48bd70e3c8e71ea69fead95
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
For a proxy-scheduled VCPU like the TUI VM, assignment to a
physical core is a runtime decision made by the HLOS scheduler,
and it may change frequently. pm_qos vote added by PVM for
specific CPUs won't be sufficient for addressing irq latency.
This change updates votes for all possible CPUs during TVM
entry and also removes the vote during exit.
Change-Id: Iab5cb5f57e2389ee57689ba2ab69394376f59788
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
After introducing avr step state, the driver checks for avr
state none before returning early. In the case where avr property
is not being set, this leads to skipping qsync programming.
This change removes this state check.
Change-Id: Ie277dd04b8913358135210131a99c598cf2145ba
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
