Currently main/aon control operation is getting trigger explicitly
from probe control with the reason that Probe IOCTL is exclusive to
sensor core. This operation is required for making sure to get the
control to hlos before reading slave id. Further post probe operation
main/aon control selection is managed by csiphy driver at the time of
acquire and release ioctl call. This will block the main camera
operation after probe ioctl successful and before csiphy acquire ioctl
call. There are some usecase where sensor needs to perform several
operation independently. To add this support moving the main/aon
selection call from probe only ioctl operation to power_up/down call
flow. This call is made upon when it is required to operate on sensor.
This change will help to give AON sensor more flexibility to perform
independently. Further CSIPHY also have the same selection process
in it's acquire ioctl operation which can help to make the hlos end
selection in combo mode scenario.
CRs-Fixed: 3084672
Change-Id: Ic1c6ad41e35605a2291e7e50ff0fe94a0ab30624
Signed-off-by: Jigarkumar Zala <quic_jzala@quicinc.com>
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
camera-kernel:
7d373a7 Merge "msm: camera: csiphy: Update the csiphy bring up sequence" into camera-kernel.lnx.dev
e415498 Merge "msm: camera: icp: Dump ICP fault/CSR registers on HFI init failure" into camera-kernel.lnx.dev
f6a93b2 Merge "msm: camera: smmu: add new flag to indicate Hw, CDM access" into camera-kernel.lnx.dev
971dc5d Merge "msm: camera: common: Update logging for better debugging" into camera-kernel.lnx.dev
a4adec8 Merge "msm: camera: sfe: Fix truncation of 64bit address" into camera-kernel.lnx.dev
11cb115 Merge "msm: camera: smmu: set 64bit mask to utilize 64GB space for camera CBs" into camera-kernel.lnx.dev
Change-Id: Ibc72134b5e7bfdc9e162553574e5a4a3da372750
Signed-off-by: Savita Patted <quic_spatted@quicinc.com>
If HFI init times out, log ICP status and CSR registers.
CRs-Fixed: 3110947
Change-Id: I611c29ee1b48f210f76750e57f38e260278b6812
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
When set, buffers will be mapped within 32-bit region
address space and in patching, if Shared or CmdBUffer is
not set for such buffers - patch the value with right shift
by 8. kmd does as below.
Map:
Shared or CmdBuffer : Mapped within 32bit.
HwAndCDMOrShared : Mapped within 32bit
others(HwAccess) : Mapped within 40bit
Patching:
Shared or CmdBuffer : as is
HwAndCDMOrShared : iova >> 8
others (HwAccess) : iova >> 8
Shared/CmdBuffer takes precedence over HwAndCDMOrShared.
CRs-Fixed: 3128094
Change-Id: Ifd9f5beaf2659f77544cd0722ef7f60d6c0684a7
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
Update the csiphy header 2.1.2 with the new bring up
sequence revision 11.
CRs-Fixed: 3127494
Change-Id: I9a3579ecd2fc2274cf9913af0ef054cc62343b0e
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
While saving iova address, we were saving into uint32 which is
truncating the address. When this address is programmed to hw,
its causing page fault. Fix by saving the iova first into
dma_addr_t which is uint64 and then calculate base and offset
register values to program to hw.
CRs-Fixed: 3128094
Change-Id: Ie8dc8cbd9848267b7b50db5ef987bd06518cc357
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
To utilize more than 32-bit address space, clients need to call
dma_set_mask_and_coherent API. When called with particular value,
the max address range thats mapped on this context bank is
min of this mask value and value_from_iommu-dma_addr_pool.
CRs-Fixed: 3128094
Change-Id: Ib48dc0b00f8e915ca7faa367bec7473aed9931b4
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
Add support to enable SFE/IFE perf counters by allowing
user to configure the counters. By default the counter
values are dumped at EOF.
To configure the counter-
adb shell cat /sys/kernel/debug/camera/ife/isp_perf_counters
adb shell "echo "ife_1_2162693" >
/sys/kernel/debug/camera/ife/isp_perf_counters"
A read on the debugfs file will list the available counters
on the target for the different HW blocks.
The change also adds support to configure CSID test bus.
adb shell "echo <reg_val> >
/sys/kernel/debug/camera/ife/ife_csid_testbus".
CRs-Fixed: 3110947
Change-Id: Idc3952e64c943acd1d1893ed24eea88cf9908100
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Force callers to say if they are using 36 bit address patching or not.
CRs-fixed: 3121782
Change-Id: I4dee25e3f73104a1be043fe18a295cd4f8447821
Signed-off-by: Karthik Jayakumar <quic_kjayakum@quicinc.com>
Print out WM information on CCIF violation.
CRs-Fixed: 3121755
Change-Id: I0fffd8cf4bc7af660f120ba1df8917cd95af64b4
Signed-off-by: Anand Ravi <quic_ananravi@quicinc.com>
Corrects the variable debug print statements for expanded memory case
in IFE.
CRs-Fixed: 3120109
Change-Id: I08e2849db21459ebaecec68a7340d8d103562743
Signed-off-by: Karthik Jayakumar <quic_kjayakum@quicinc.com>
Due to hw limitation, if the required RDI buffer output is
Plain16_10/12/14, BUS cannot conver CSID unpacked MSB data
into LSB aligned while writing the buffers. So keep CSID out
as unpacked LSB data if the final RDI output buffer format
is Plain16_10/12/14. This will have limitation in using RDI
data going into LCR/PDAF.
CRs-Fixed: 3118104
Change-Id: I9193530ec549b4658a058ae71eed4f31653bd88e
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
Currently lane specific general register programming is structured
with lane index basis. This is not required as general register
needs to program without any condition. This change updates structure
of this programming register. Also, array size calculation is replace
with more intutive way rather to manually enter the size everytime.
CRs-Fixed: 3117726
Change-Id: I5e57f37bf2025b37f23c10b835fd31ddfe986cee
Signed-off-by: Jigarkumar Zala <quic_jzala@quicinc.com>
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
To avoid concurrent access to the device timers while
stopping them, keep the stop call protected with hw
mutex.
CRs-Fixed: 3080397
Change-Id: If0a5226536e3a3c14738811965511225d1a96f08
Signed-off-by: Tejas Prajapati <quic_tpraja@quicinc.com>
Extension of Let's do a reset (LDAR) for ICP to include more info.
CRs-Fixed: 3105929
Change-Id: I5fee181d009a8d69e8d3e673a552b289f72fb4aa
Signed-off-by: Joshua Florez <quic_jflorez@quicinc.com>
camera-kernel:
48c1c34 Merge "msm: camera: csiphy: Add lane enable register capability" into camera-kernel.lnx.dev
f354ed9 Merge "msm: camera: isp: Keep the data in MSB while unpacking at CSID" into camera-kernel.lnx.dev
Change-Id: If82b6a657c246dfc1872ef65acc17e939da4ec32
Signed-off-by: Savita Patted <quic_spatted@quicinc.com>
BUS, SFE pipeline(xCFA), PDAF/RDI-LCR pipeline expects the
incoming valid data to be in MSB. So, if RDI data is unpacked
to PLAIN_16 at CSID out, keep the valid data in MSB.
For final out formats PLAIN16_10/12/14/16 formats, unpack
data at CSID and keep in MSB and use wm pack with LSB write,
as LCR/PDAF can be enabled with these final out formats and
expects data in MSB.
CRs-Fixed: 3118104
Change-Id: Idb64d809ea006192eb29bb9bb57c5c12a6e8b136
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
Add and handle lane enable register offset programming independent
than common control register array.
CRs-Fixed: 3117726
Change-Id: I7a9cfe41cb425143bf2be6c48de47dfb5e117aae
Signed-off-by: Jigarkumar Zala <quic_jzala@quicinc.com>
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
To configure CP mask correct version check needs to be
used against CPAS hw version. Currently csiphy driver
is checking platform version to make the decision.
This change update this check with CPAS hw version check.
CRs-Fixed: 3048249
Change-Id: Id023f5cc0252b47c274dfed9d93e7f49a3d0ab49
Signed-off-by: Jigarkumar Zala <quic_jzala@quicinc.com>
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
After flushed, KMD reports ERR including isp, actuator, sensor, flash.
However many CRs don't have fatal KMD error log, but participant is KMD.
Remove the non-fatal KMD error log.
CRs-Fixed: 3095401
Change-Id: I0e5e370c0c4d1daceb72d9eed8d0c45baad5179e
Signed-off-by: Wang Kan <quic_wkan@quicinc.com>
camera-kernel:
c8e56da Merge "msm: camera: cdm: Fix the CDM Reg dump" into camera-kernel.lnx.dev
e63fee2 Merge "msm: camera: isp: Add support for the new error codes" into camera-kernel.lnx.dev
Change-Id: I5a62e828fbaa686af2b2dd84f1ad879cf6562b5e
Signed-off-by: Savita Patted <quic_spatted@quicinc.com>
Add support for more error codes in the kernel code to
report more errors to user.
CRs-Fixed: 3112574
Change-Id: I6eef2bd73d5ff7cac9d0ed95682c76c4438cfa47
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
We acquire RDI0 by default for SFE cases without RDI out ports.
We need to skip RDI0 resource acquire if RDI0 is already acquired
previously.
CRs-Fixed: 3092119
Change-Id: Icb62b07f03b1ac14560ca152e6fca479a4acb1a4
Signed-off-by: Chandan Kumar Jha <quic_cjha@quicinc.com>
Updates board list of supported msm-mmrm boards to include kalama.
CRs-Fixed: 2980570
Change-Id: I182ef8b56b67c24d1ad9c4b23f475782f93e8aed
Signed-off-by: Karthik Jayakumar <quic_kjayakum@quicinc.com>
Combine the num_exp for sHDR EPCR case, and we can
override the mode switch related parameters only
when the mup is enabled in new req.
CRs-Fixed: 3106141
Change-Id: I1bd0b38402962ca598f2e5c6bd528a0af2adc55f
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
Extension of Lets do a reset (LDAR) to include more information
in dump with more dump output enhancements.
CRs-Fixed: 3068971
Change-Id: I6b61bcf546e32c096e45c511faf64514ff391e62
Signed-off-by: Joshua Florez <quic_jflorez@quicinc.com>
Fix few incorrect log and add ctx id for
irq handling log.
CRs-Fixed: 3101894
Change-Id: Ibd2783124ed6354a379b9804e6e6bc01f2ab6fb3
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
Add data struct for reporting v4l2 event on page
fault. Upon receiving the event, userspace is
expected to abort, and all kernel drivers are shut
down. when Titan power on the next session, CAMSS
will undergo async reset.
CRs-Fixed: 3109439
Change-Id: I518148baa2414fd072b874200a408589332f95ec
Signed-off-by: sokchetra eung <quic_eung@quicinc.com>
Kailua tpg has some extra register for ir/xcfa/shdr overlapped.
These register data support is added as part of this change.
CRs-Fixed: 3086082
Change-Id: If044b336a87de931f6d512c52895e65c85d10863
Signed-off-by: Rishab Garg <quic_rishabg@quicinc.com>
Add interleaving format to support 2PD for tpg0.
CRs-Fixed: 3100297
Change-Id: Ic59c4cec0990faa3d70f45aa34baebaa33e08b2b
Signed-off-by: Rishab Garg <quic_rishabg@quicinc.com>
For SFE 780, Input to SFE from CSID for single xcfa use cases
is RDI0.
This commit changes the acquire logic to acquire RDI0
in case of SFE context for single ISP/SFE use cases and IPP
for dual ife cases.
CRs-Fixed: 3092119
Change-Id: I7e7ba0438435c6fe7a8b0d22f7c08b7ce4da1819
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
