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Raviteja Tamatam
a2d05648c2 disp: msm: sde: fix error message in sde_crtc_opr_event_notify
Fix error message arguments in sde_crtc_opr_event_notify
function.

Change-Id: Ibfb4b4a298bc9ec8128061a103ce6500ec1cce29
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
2022-11-07 10:39:19 -08:00
qctecmdr
f62878f3ab Merge "disp: msm: dp: Add abstract and wcd939x aux switch support" 2022-11-03 19:18:25 -07:00
qctecmdr
8a9455aa23 Merge "disp: msm: sde: use panel dimension on full frame RC ROI" 2022-11-02 02:17:05 -07:00
qctecmdr
940ff2a8a7 Merge "disp: msm: sde: fix to avoid creating output hw-fence for CWB" 2022-11-02 02:17:05 -07:00
Nisarg Bhavsar
4a2e5b3fe1 disp: msm: dp: Add abstract and wcd939x aux switch support
Add functionality to change which aux switch is used
at compile time for different targets. Add wcd939x
switch support.

Change-Id: Iced3b11733009680063790dfa8f180b19002f963
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
2022-11-01 19:15:01 -07:00
Raviteja Tamatam
7a1d4a2ec8 disp: config: add pineapple TUI configuration files
Add pineapple TUI build configuration files.

Change-Id: I920a247ee191efc7fae2e74b31a773b6110e6c36
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
2022-11-01 14:18:04 -07:00
Amine Najahi
de2108f9b5 disp: msm: sde: use panel dimension on full frame RC ROI
Currently, RC is using displayh and displayv variables
which are pointing to the LM dimension on a full frame
setting. If DS is enable and HW RC was not disabled the
the full frame ROI will not match the panel resolution
and cause an invalid hardware configuration.

This change uses the height and width values coming
from the mode information when a full frame ROI is
detected.

Change-Id: I274d15cbca61076ea7e95a984f907201e97b76ec
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-11-01 05:28:11 -07:00
Ingrid Gallardo
e778c5e3a6 disp: msm: sde: fix to avoid creating output hw-fence for CWB
Current code creates an output hw fence for any virtual
connector with a retire fence attached. This is a problem
for CWB, where the output-fence should be handled as a
sw-fence as current hw can only support a single hw-fence
per ctl path.
Fix this issue by adding a check to only create a retire
output hw-fence for virtual connectors that are not CWB.

Change-Id: I5863282d24ef8940b1f45c1fbd7584f91d28f0b8
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
2022-11-01 05:27:51 -07:00
Andrew Bartfeld
5dcee7c010 disp: msm: dp: avoid releasing vcpi for active crtc
In MST atomic check function, add a check to ensure it's a disable call
before releasing vcpi slots to ensure atomic_release_vcpi_slots() and
atomic_find_vcpi_slots() are never called in the same atomic check
as mentioned in the kernel docs.

Change-Id: I36cf689b4d3bf9d2469a6c402b6377a667f01c12
Signed-off-by: Andrew Bartfeld <quic_abartfel@quicinc.com>
2022-11-01 05:27:16 -07:00
qctecmdr
1c465e0434 Merge "disp: msm: dsi: clear the panel esd_recovery_pending in power on commit" 2022-10-31 20:56:57 -07:00
qctecmdr
ba03a764fe Merge "disp: msm: dp: enable aux switch from display HPD handler" 2022-10-31 20:56:56 -07:00
Srihitha Tangudu
219652f3a8 disp: msm: dsi: clear the panel esd_recovery_pending in power on commit
Currently the panel esd_recovery_pending flag is cleared for every mode
set. The ESD recovery completes only after the suspend and resume. Clear
the flag only during power on commit.

Change-Id: I97e370feba0aad34558e4675168b4bcb7f5901ca
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
2022-10-30 23:37:36 -07:00
Sandeep Gangadharaiah
c76df5605c disp: msm: dp: enable aux switch from display HPD handler
Currently, aux switch is enabled by usbpd handler before
handing over the control to dispaly HPD handler. However,
in some scenarios there is a chance that altmode would
directly call into display HPD handler bypassing the usbpd
handler. This would lead to aux errors since aux switch
is not enabled. This change will enable aux switch in
display HPD handler which would avoid the resulting aux
errors. This issue is a regression caused by this change
b6466ca7f597396cd2ecb3623d059435dfb0e4c6.

Change-Id: I425991ba95b22411740f88cba5ca2083d13969e1
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-10-29 16:23:35 -07:00
Amine Najahi
5b1d909312 disp: msm: sde: disable RC in case of configuration mismatch
Currently when there is a modeset and usermode does not disable
or reprogram the RC mask, driver will compute an invalid configuration.

This change checks the RC mask with panel resolution and disables
RC HW internally if there is a mismatch.

Change-Id: I0e6afcf38cfc9165a6c0d2c12bfbc7b2b5f2ce65
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-10-29 16:23:28 -07:00
qctecmdr
abdb501164 Merge "disp: msm: sde: pass sde_enc to sde_encoder_control_te" 2022-10-28 18:12:44 -07:00
qctecmdr
562083b5a2 Merge "disp: msm: sde: include drm_edid.h" 2022-10-28 13:03:46 -07:00
Nilaan Gunabalachandran
4f6e8ea41b disp: msm: sde: include drm_edid.h
This change adds the include for <drm/drm_edid.h> required
for the display driver in kernel 6.0.

Change-Id: Ie4c765900a1ae13e1fbb56e458109b725b36748d
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2022-10-28 12:40:27 -04:00
qctecmdr
086d6e622a Merge "msm: drm: sde: Add support for UCSC via AHB programming" 2022-10-28 08:05:48 -07:00
qctecmdr
354c9c0b46 Merge "disp: msm: dp: Convert clock operations to byte2 ops" 2022-10-28 08:05:48 -07:00
qctecmdr
dd39b5f3d1 Merge "display: msm: sde: add offsets per ctl for lut dma" 2022-10-27 19:50:51 -07:00
qctecmdr
7301c101d0 Merge "disp: msm: dsi: add ctrl version support for pineapple" 2022-10-27 19:50:50 -07:00
Sandeep Gangadharaiah
e4e277ad36 disp: msm: dp: Convert clock operations to byte2 ops
Convert clock operation to byte2 ops to meet DISPCC requirement.
Clock unit is changed from KHZ to HZ. Added link clock parent as
freq table is no longer supported in byte2 ops.

Change-Id: Icf5a595708040e8afefecebe7f371bb832d6673e
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-10-27 15:39:14 -07:00
qctecmdr
4522999001 Merge "disp: msm: sde: add support for 45deg dir & corner detection" 2022-10-27 14:20:17 -07:00
Shamika Joshi
33dcc003f6 disp: msm: sde: add support for 45deg dir & corner detection
Pineapple target adds support for 45deg Directional & Corner
Detection features for Qseed6. This change adds support for
enabling these features through ahb & lutdma programming,
and updates the UAPI as well.

Change-Id: I7910d840cc4e5d1a7ce9444a41e189171487dbca
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
2022-10-26 14:44:05 -07:00
GG Hou
19a9abf064 disp: msm: dp: update MST first link slot information
update MST first link slot information as upsteam interface

Link: https://patchwork.freedesktop.org/patch/msgid/20211025223825.301703-3-lyude@redhat.com

Change-Id: I871504942d596ee742e5481be9c8b6cf0f50e8ac
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2022-10-26 14:11:37 -04:00
Nilaan Gunabalachandran
db39fcc5bc Revert "disp: msm: compile pineapple msm with mm-drivers"
This reverts commit 473453a8d9.
This change decouples mm driver and display driver until mm
driver compilation is enabled.

Change-Id: I1b462d059b26242b6b77b0bc6ad990d7dabcb0ac
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2022-10-26 12:16:08 -04:00
Shamika Joshi
4cc3c88474 disp: msm: sde: pass sde_enc to sde_encoder_control_te
Pass sde_enc to sde_encoder_control_te instead of drm_enc,
as all callers have access to sde_enc.

Change-Id: Ic61b78c9e8d1ab2ed6e371c19a72367efbb6e5ee
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
2022-10-25 21:06:48 -07:00
Shamika Joshi
f28d9e0a6a disp: msm: sde: add support for INTF WD long term jitter restore from ipc
Change adds support for storing the INTF watchdog timer long term jitter
curve state. The state before collapse is stored in wd_jitter and
restore back during power restore.

Change-Id: Id83b5cc754daea89d7844ab67b38e12199525ff8
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
2022-10-25 21:06:39 -07:00
Kirill Shpin
60965fdeae disp: msm: dsi: add ctrl version support for pineapple
Added dsi ctrl version 2.8 support for pineapple hardware

Change-Id: If9beb77c53d70d94b498b5b837c26892a4df9089
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
2022-10-25 09:31:49 -07:00
Gopikrishnaiah Anandan
8da5ae2855 display: msm: sde: add offsets per ctl for lut dma
DPU hardware is being updated to add per ctl offsets for lut dma.
Change adds support for per ctl offsets.

Change-Id: I2ee1d6ba1a53dea20a3f422ccecb33910fbaf361
Signed-off-by: Gopikrishnaiah Anandan <quic_agopik@quicinc.com>
2022-10-24 12:51:31 -07:00
qctecmdr
38c0d4cdba Merge "disp: msm: sde: enable uidle on pineapple target" 2022-10-24 12:37:21 -07:00
qctecmdr
f320be5d5e Merge "disp: msm: sde: avoid setting plane qos_dirty during cwb modeset" 2022-10-24 12:37:21 -07:00
qctecmdr
48dc1006fd Merge "disp: msm: sde: improve qsync trigger window accuracy" 2022-10-24 12:37:21 -07:00
Alisha Thapaliya
c2364bdd17 msm: drm: sde: Add support for UCSC via AHB programming
Add support for UCSC block parameters that includes unmult,
IGC/GC modes, CSC coefficients, and clamps.

Change-Id: I3ef4b729e9c973a98d53dc583233bf5e004035fa
Signed-off-by: Alisha Thapaliya <quic_athapali@quicinc.com>
2022-10-24 10:53:36 -07:00
Amine Najahi
88a24f8c45 disp: msm: sde: improve qsync trigger window accuracy
Currently, panel jitter and loss of precision are not
compensated when calculating the trigger window size
for a QSYNC panel. These errors can be signigicant on
panels supporting very slow frame rate (10 Hz).

This change improves fixed point calculation and take
into account panel jitter when calculating the minimum
qsync time period.

Change-Id: Ibe620862afbd853580992fccec09cac8307b92bd
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-10-24 07:29:31 -07:00
Amine Najahi
16f59151af disp: msm: sde: override qsync read pointer during IPC
Currently, when there is an idle power collapse HW resets
the internal read pointer value to 0. This causes the trigger
window to be out of sync when power is restored until the
next vsync is received.

This change overrides the internal read pointer value to
the maximum qsync timeout value on restore and defers frame
trigger to next vsync.

Change-Id: Ibdad3f8eb367136ee0d766bed10742a281e36b4e
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-10-24 07:29:24 -07:00
Veera Sundaram Sankaran
1b1618ed36 disp: msm: sde: avoid setting plane qos_dirty during cwb modeset
The encoder modeset updates all the plane's qos_dirty flag attached
to the crtc to make sure the qos params are updated during seamless
mode-switch cases like fps or resolution switch. But this is not
required for cwb encoder modeset as it does not have any effect on
the planes attached to the main display. Add check to avoid this
reprogramming.

Change-Id: I1ab7a71971b7200a50e6643407327734b1c9cbc5
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-10-24 07:29:15 -07:00
qctecmdr
83cb3d44af Merge "disp: msm: compile pineapple msm with mm-drivers" 2022-10-22 10:49:22 -07:00
Alex Danila
473453a8d9 disp: msm: compile pineapple msm with mm-drivers
Enabled compilation of msm_drm with mm-drivers components.

Change-Id: Id2f15b314748f9a1a9966625cea98fa4b3855e87
Signed-off-by: Alex Danila <quic_eadanila@quicinc.com>
2022-10-21 14:02:12 -04:00
Nilaan Gunabalachandran
6ae388a1c1 disp: msm: sde: enable uidle on pineapple target
Pineapple target adds support for writeback contributing to
fal status. This removes the need to signal fal10 veto in those
usecases. In addition, it is no longer needed to program uidle
active per ctl path.

Change-Id: I5e3509fa6399d212563322d51eba04c38a41e9b8
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2022-10-21 12:03:39 -04:00
qctecmdr
03f6a06942 Merge "disp: msm: sde: enable WB rotation feature for pineapple target" 2022-10-20 12:29:12 -07:00
qctecmdr
f378c8b20e Merge "disp: msm: sde: add line counter logging" 2022-10-20 12:29:12 -07:00
qctecmdr
2d49ae68e6 Merge "disp: msm: sde: cache cwb enc mask to use during seamless transitions" 2022-10-20 12:29:12 -07:00
Prabhanjan Kandula
973fb33096 disp: msm: sde: enable WB rotation feature for pineapple target
This change enables the WB rotation feature support for pineapple target.

Change-Id: Ib222c2b2996a40c72414c6c3a581916b95ebffd6
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
2022-10-19 11:24:18 -07:00
Prabhanjan Kandula
bdfc560f6e disp: msm: sde: extend DNSC validation for wb rotate
Atomic validation checks added for DNSC feature need to
be extended considering WB rotate feature enable.

Change-Id: Iff908da062280418536d00a5fcdeb99939267659
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
2022-10-19 11:24:11 -07:00
Prabhanjan Kandula
c3991049c1 disp: msm: sde: add support for new QoS mode of WB rotation
This change adds support for new dynamic QoS mode for WB rotation
which is required to achieve rotation output available at required
rate to meet real time use case. Though traffic shaper can be
disabled in dynamic QoS mode, part of traffic shaper algo to track
WB operating speed is enabled and WB generates creq priority
based on current ouput rate compared to targetted ouput to help
meeting real time use case requirement.

Change-Id: I98c2dcae53f1b175dc49b40238b9da33e95717a6
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
2022-10-19 11:24:04 -07:00
Prabhanjan Kandula
3128214eac disp: msm: sde: add rotation support with writeback block
MDSS 10.0.0 HW is capable to rotate input image in WB hardware
block. WB hardware can only perform rotation of clockwise 90 degrees
and this can be used to achieve the required 2D rotation by adding
appropriate FLIP transformation to the SSPP. This change adds required
software support in display driver to excericse input image
rotation through WB block.

Change-Id: Ia5c2fc84eabb68f29d130333316527b60d02cbc7
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
2022-10-19 11:23:58 -07:00
Prabhanjan Kandula
f3c2c5e37d disp: msm: sde: add WB rotation output color formats
MDSS 10.0.0 HW supports rotation of input image with
writeback HW but output color formats are restricted to
32 bit uncompressed A5X tile formats. This change exposes
the supported WB output color formats to client for WB
rotation usecase.

Change-Id: Ic52e6ee4ab882b7dad6edd0daa91b593afbcae01
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
2022-10-19 11:23:50 -07:00
Prabhanjan Kandula
4cca89d615 disp: msm: sde: add drm properties required for wb rotation
This change installs required drm properties for writeback
connector to implement rotation with writeback hw in mdss.

Change-Id: I85ed359d06ff4bafee85a4bfa5b8a99774311e60
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
2022-10-19 11:22:49 -07:00
Raviteja Tamatam
22a3c5a842 disp: msm: fix display compilation for 6.0 kernel upgrade
Fix display compilation issues for 6.0 kernel upgrade.

Change-Id: Ied1940e653ceaa1de18a8aedeab01197c235603c
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
2022-10-19 11:04:22 -07:00