While same spinlock can be used to protect a critical section
in both irq-handler and in non-irq context, in non-irq context
it is mandatory to use irqsave version of locking api to disable
irqs locally on the particular cpu. Otherwise, this could lead
to a deadlock if a non-irq thread holding the spinlock and irq
handler is scheduled on same cpu.
This change replaces physical encoder spinlock locking with
irqsave version of locking api in the non-irq context.
Change-Id: If73b4c995b75e9499d79fbe969d426427fd3a9d1
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Add case tags in eventlogs in cmd_prepare_for_kickoff to
help in differentiating the logs in this function.
Change-Id: Idce10e715c77340175d124ec3ef7ecc30c95a0af
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Introduce a new connector property called “EPT_FPS” for the cmd
mode panels. User space will set the “EPT_FPS” based on the
intended content fps, relative to the last retire fence timestamp
as calculated by Surface flinger. Program start window based
on the Expected Present Time fps.
Change-Id: I24b93e0f941af9fb2422b2484328254d04a1acbe
Signed-off-by: Shirisha Kollapuram <quic_kshirish@quicinc.com>
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Currently, QSYNC sim panels are not fully emulating panel
side logic to allow different refresh rate depending on when
the frame is received by the panel.
This change adds the logic to reconfigure the TE watchdog at
different frame rate depending on when the frame is sent to the
simulated QSYNC panel.
Change-Id: I3f0de73976a0fc5748a76c4f7ab00205d1af9a1b
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Modify the default INTF TE sync threshold config in cmd-mode to
32-bit max based on the INTF TE 32-bit support.
Change-Id: I963ffa8ae37bce0e85deb335609857c17e32d6b0
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Currently, when there is an idle power collapse HW resets
the internal read pointer value to 0. This causes the
trigger window to be out of sync when power is restored
until the next vsync is received.
This change reads the panel read pointer and overrrides
the internal register to allow a frame to be picked up in
the current vsync cycle, but defers it to next vsync if it
comes later than the safe trigger window.
Change-Id: I741a91edcddc105eda34d875e8e1c32933b83d71
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Starting with HW-Fencing, the frames hw kickoff
can take longer to trigger, given that HW will wait for the
input fences signal. Therefore, this change increments
the time-outs to wait up to ~10 secs, which corresponds
to the current input dma-fences timeout. This ~10secs
wait is given in intervals, where the dma-fence is also
checked, so in case that the client producer of the fence
signals the dma-fence, but misses the hw-fence signaling,
Display driver can handle this case and do a sw-override
to start the fetching of the incoming frame without waiting
for the input hw-fence ipc signal.
Change-Id: I6fcacbbaa79ca9847da616bd52efdda4bb8fccae
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change adds support for dynamically enabling and disabling
additional physical encoder IRQs.
Change-Id: I500fa69d1b8b8df39fd608391c906257efdea63b
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Change adds support for storing the INTF watchdog timer long term jitter
curve state. The state before collapse is stored in wd_jitter and
restore back during power restore.
Change-Id: Id83b5cc754daea89d7844ab67b38e12199525ff8
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Currently, panel jitter and loss of precision are not
compensated when calculating the trigger window size
for a QSYNC panel. These errors can be signigicant on
panels supporting very slow frame rate (10 Hz).
This change improves fixed point calculation and take
into account panel jitter when calculating the minimum
qsync time period.
Change-Id: Ibe620862afbd853580992fccec09cac8307b92bd
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Currently, when there is an idle power collapse HW resets
the internal read pointer value to 0. This causes the trigger
window to be out of sync when power is restored until the
next vsync is received.
This change overrides the internal read pointer value to
the maximum qsync timeout value on restore and defers frame
trigger to next vsync.
Change-Id: Ibdad3f8eb367136ee0d766bed10742a281e36b4e
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Add logs to track the read/write line counters
and tear check configuration during key events.
Change-Id: Ife8afecc63a9008a8d9fc746d0ec8579a311b335
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
This change adds support for INTF TE using 32 bit values and
single update per TE. These features help ensure that during
QSync mode the TE does not overrun in certain late trigger uses.
Change-Id: I893d0cde81320c3f17604694a4d8ee52b29a9425
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
When qsync is enabled with a large threshold start window, there
is a chance that two frames can be latched by mdp HW in single
vsync window. This change overrides the tearcheck rd_ptr_val
to a value larger than the end of the Tear check start window
to ensure new frame is not latched in current vsync window.
Change-Id: I21273f0bca83747210792b911e964dfd2d50079f
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This change updates the autorefresh disable sequence to manually
trigger output hw_fence during the transition. This is required
since on the last autorefresh frame HW will not trigger the output fence.
Change-Id: I6789fc6b51421524f88dcbdd1a063ae947646ae4
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change adds the value of hw-fence ready to
event logs for video and command modes.
Change-Id: I40a2e886a3b95e8853efcbdddf7fd9f6ce48eb9b
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Disable the autorefresh during encoder disable to avoid any
pending frame transfers while disabling. Additionally, handle
frame_done for new autorefresh frames to signal the fences and
proper accounting of pending_kickoff counter.
Change-Id: I8af114972b19ccdf0edab6b4c454ee90b4e8d8cf
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change avoids null pointer dereference in different APIs.
Change-Id: I01eba9d64fa4ba2fd81f7f39f586867e22d66771
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
With MDSS 9.0.0, s/w relies on the ctl-done-irq which signifies the
frame done for the ctl path. Avoid unnecessary waits during
tx-done/commit-done on the individual physical encoders when ctl-done
feature is enabled.
Change-Id: Ie5e8b08c47a4778dfa03a87dbbae8daf6a738e6a
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This change reinitializes the sde_crtc->mixers when CTL
datapath switch occurs during mode set and RM allocation
of CTL hw block is changed. This initialization is required
for CTL_LAYER programming to trigger on the new CTL allocated
from RM.
Issue case:
1. Primary Display is using CTL_0 and it is reserved.
2. Secondary Display is using CTL_1. On suspend, RM adds
CTL_1 into the free list.
3. External Display is powered on, RM allocates CTL_1 hw blk.
4. Secondary Display is powered on, RM allocated CTL_2 hw blk.
5. External Display is suspended/unplugged, RM adds CTL_1 into
the free list.
6. When any mode_set(say fps switch) occurs on secondary, RM
allocates new resources and CTL_1 is allocated.
sde_crtc->num_mixers is non zero, so all the layer programming
happens on CTL_2, but CTL_1_FLUSH bits are programmed causing
hw timeout issue.
Change-Id: I5f1f52b7673740c48b249ab4d36e80b7a1d3db96
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
From Kalama, the HW scheduler abstracts the low level
PP_DONE/WB_DONE interrupts and generates a common
CTL_DONE interrupt per hw ctl. This saves the software
the irq latency delays to process the frame complete
operations when multiple encoders are involved.
If supported, this change enables and waits for the
CTL_DONE interrupt instead of PP_DONE and WB_DONE.
This change adds support to wait for CTL_DONE irq in
only command mode panels as we don't drive two WB blocks
with single CTL.
Change-Id: I084d6bfb6a9fb0b48f912fe5787401c460ec5b56
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
From MDSS 9.x, the pp-done wait requirement as part of autorefresh
sequence is not required. Add a catalog flag to avoid the wait for
mdss 9.x+ and to support backward compatibility.
Change-Id: Ieca008d3d6ef0f7326b65433ef42ed9f49a94f87
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
The sde_hw_blk was meant to be a generic base object for all
SDE HW blocks, however, it enforces using a common set of ops
which is not practical when blocks have different capabilities.
Since this object was never used as intended and is not doing
anything functional today, remove the dead weight.
Change-Id: If76006c1ae5c62e8d7d77b100837dbaf6c661bd3
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
Current timeout values in sde driver for vblank, kickoff and
frame complete timeouts are fixed and can be much lower than
a vsync incase of low refresh rate display. Compute timeouts
based on refresh rate for low refresh rate displays.
Change-Id: I9dda41feb15446de7451824e185321de421ad575
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
This change adds support for qsync min refresh rate per
timing mode and populates qsync min refresh rate based
on the current fps when qsync is enabled.
Change-Id: I191d1d72e95dd065c8c0b56a6100104c00c6d8f6
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
VA minidumps supports to add any allocated variable or data to
minidumps. Add panic notifier and wrapper function to add
sde data to minidump va. Add event log, register log, register dumps,
debug bus and different sde variables and states info to minidump.
Change-Id: If54da0b7067df17877e4da645d82f1705baa3f6d
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
Move esd check to write pointer wait instead of during
write pointer timeout. With this change display will avoid
improperly signaling a retire fence and allowing two flushes
to happen within a single vsync in cases where ESD failure
is happening.
Change-Id: I6fbd76a2f6b47d3237039f66a3b1edd1f72a0a1d
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
In SDE driver auto refresh disable sequence, seq2 execution
is possible. Avoid error log for every iteration and log
only when seq2 fails.
Change-Id: I1e2b3dcc775bf5fef28fe2e0c6846d3940a2bad1
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
In the event of panel dead scenario, it is possible to receive a
mode set call before the panel has recovered. When this happens,
display should select watchdog TE as the vsync source.
Similarly when detecting a write pointer timeout, if the panel is
dead then watchdog TE should be or has already been configured and
display should not make a change to this vsync selection.
Change-Id: I732c75e54d734b00889151b914b0749ae1f27d08
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
While setting up vsync source, display info is used to decide whether
or not watchdog TE should be used. This change passes display info
as a parameter to vsync setup rather than using the encoder's display
info which is not updated in the case of panel dead error.
Change-Id: I928ee2012eec7bf63f4ba3538082bc3e47d5e99d
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This change increases the kickoff timeout in doze and
doze suspend usecases. This avoids false timeouts seen
in doze due to rscc static wakeup configured at a different
fps from actual panel TE.
Change-Id: I11c94eb40d4dbbc3d95b8268b007580599ee90fd
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
This change initializes a variable as null to account for cases
when it is not set. This change also ensures proper pointer
checks before attempting to access function pointer.
Change-Id: I2f06a0877293668e80bee9d9b82d412476dc5184
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Remove idle time from the Qsync calculation as this was added by
mistake to allow writes to complete just before the next TE but
this causes tearing. Also, to ensure tearing doesn't recur,
round down the threshold lines to the nearest multiple of 4, and
remove a couple of extra lines to compensate for potential
latencies.
Change-Id: I8a53a989e26cbd7f0e2b94caa8df8f5bee3ad26c
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
SDE RSCC solver state and autorefresh enable concurrency
is not supported. This change moves the rscc solver state
to disable to avoid concurrency. It also resets the autorefresh
software structure state when encoder is disabled. This allows
autorefresh reconfiguration with next encoder enable.
Change-Id: Idb8c722c823d9f46d3cd03e1b046da69c8d88fc4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
In dual DSI cases sde_encoder_helper_phys_disable needs to be
called only for master encoder.
Change-Id: If2d327a4800914fe365c6877bf7854275a4434ae
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
Currently, SDE_DBG_DUMP takes any number of hw block names along with
few defined strings as arguments. This set of arguments is used to
determine which HW block registers needs to be dumped. Move to a
blk bitmask to avoid passing a large set of arguments. The bitmask is
split based on the clks required to access the HW block for ease of use.
The lower 0-23 bits are used for HW blocks which can be accessed by just
enabling the MDP clks. DP is kept separate as it needs DP specific
clks to be enabled. Add a debugfs node through which the mask can be
modified, which can be useful while using the debugfs dump option to
force a panic.
As part of the change, remove in-log/in-mem enable mask debugfs node
for every debugbus and use a single node to control the logging
mechanism for all the HW blocks debugbus.
Change-Id: Ibb6354b3e3265c9911104bb0f964616eb8a898c9
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Calculate line_time once during modeset and allow
each plane to use it instead of calculating for each frame.
It also simplifies the line_time calculation for
command mode display.
Change-Id: I94ce29eec94bfdbee9016fbf93378661ebf79c03
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
