When VSYNC interrupts are delayed due to irq latencies, there is a
possibility that the timeout handler checking the irq status and the
irq handler clearing the status bit happening at the same time on
different CPU cores. This is reported as an error, though there is
not actual issue. Handle this case, by adding an additional ctl-flush
register check in the vsync timeout handler. As part of the change
add error/eventlogs in commit-done wait failures.
Change-Id: Ie7e30dc4ef1e50651cee9015cd3f2caeacf47e5f
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Log the vblank timestamp during vblank callback. This will be
useful in calculating the precise difference between the vsync
while debugging. As part of the change, remove the vblank
counter logging in sde_crtc as it floods the logs with 4 entries
for each vblank request.
Change-Id: I6b532ad657581fb2a34318541acbd81a44858819
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change adds support for triggering output
hw fence upon programmable line count.
Change-Id: Ie4b8252e4f9a448a8c11d17696b9bb0ded81b04b
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Starting mdss 9.0, dpu supports triggering
the frame fetch through hw-fencing. This change
adds support for this hw-fence feature.
Change-Id: Icc7d0b69fc2a51103d14612f5ac89b44a47ed826
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change collects the OPR, MISR values. If the values are
different than the previous then notify to client with custom event.
Change-Id: I2546439be1f665d90e6505d65283d28096bf7cdd
Signed-off-by: Akshay Ashtunkar <quic_akshayaa@quicinc.com>
This change updates vsync source as part of rc post modeset. For some
use cases like idlepc with DFPS, vsync could be configured for
previous fps and can cause timeouts during next frame.
Change-Id: I110fd958d2970eaca50ace0e72c4faea3fc64ce8
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
Add line insertion support for sspp, this is used to support
display with external splitter. Line insertion logic checks
the difference between screen logical height and physical
height. If any difference is observed adds dummy and active
lines on screen.
Change-Id: Ieec322273df000a53fb39e05174c2d67c3c2da81
Signed-off-by: Rajesh kv <quic_kvrajesh@quicinc.com>
Disable the autorefresh during encoder disable to avoid any
pending frame transfers while disabling. Additionally, handle
frame_done for new autorefresh frames to signal the fences and
proper accounting of pending_kickoff counter.
Change-Id: I8af114972b19ccdf0edab6b4c454ee90b4e8d8cf
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Avoid various possible nullptr dereferences
and check validity of index before accessing
arrays. Addresses issues highlighted by
static analysis.
Change-Id: I5abfbc8c4cacb56e9decc3a6339ab0fa3a63b606
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Currently aggresive idle-pc entry is only enabled in
case of doze-suspend mode. Extend the support to doze
mode as well.
Change-Id: I8e9e0e116bb65a1aec0180bf9bc10bed99d4a137
Signed-off-by: Govinda Rao K S <quic_gkarikur@quicinc.com>
MDSS 9.0.0 added support for logging MDP_VSYNC timestamp. Use it for
video-mode panels and rely on PANEL_VSYNC timestamp for cmd-mode panels
as it relies on external panel TE.
Change-Id: I09b25d893075bee7cb2da98d4c4b4e54eb09bd6e
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This change avoids sde error during fal10_veto override enablement
for targets with uidle disabled and early returns in such case.
Change-Id: I491952615d7b3cbd70d35b4a90ee8d27ab56c2ad
Signed-off-by: Yojana Juadi <quic_yjuadi@quicinc.com>
This change updates copyright description with correct
license marking as per the guidelines.
Change-Id: Ia74b721e78afcc7f8e88bcbccfcf15430111ec37
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
When cwb is enabled enable software override for fal10 veto to
block fal10 entry as MDSS can keep asserting uidle if there
are no fetch clients like dim layer only usecase.
Change-Id: Ief51499d370c20fcbdda79576aee0179578650fd
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Use #if IS_ENABLED() instead of #ifdef for configurations as vendor module
guidelines.
Use #if IS_ENABLED(CONFIG_XXX) instead of #ifdef CONFIG_XXX to ensure that
the code inside the #if block continues to compile if the config changes
to a tristate config in the future.
The differences are as follows:
1.#if IS_ENABLED(CONFIG_XXX) evaluates to true when CONFIG_XXX is set to
module (=m) or built-in (=y).
2.#ifdef CONFIG_XXX evaluates to true when CONFIG_XXX is set to
built-in(=y) , but doesn't when CONFIG_XXX is set to module(=m).
Use this only when you're certain you want to do the same thing
when the config is set to module or is disabled.
Change-Id: Ia806b9b01ad8414d0e4de027a382cb68e7fb4a6a
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
During virt disable call, sde_enc master was used without checking
for null condition. It results in crash. This change adds required
null pointer check for sde encoder current master before dereferencing
to avoid crash.
Change-Id: I69ee17017712ea3549bfefce5975a564a5a8c2e9
Signed-off-by: Yojana <quic_yjuadi@quicinc.com>
msm/sde/sde_encoder.c
_sde_encoder_update_rsc_client()
sde_encoder_prepare_for_kickoff()
msm/dsi/dsi_drm.c
dsi_bridge_mode_fixup()
Lower the cyclomatic complexity for this function by splitting
the work into helper functions.
Change-Id: I2285809a33078e29989a6b44800c18342aa24170
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
pm_runtime_get_sync increases the usage_count refcount immaterial of
success/failure of the call, leading to invalid refcount on failures.
Use pm_runtime_resume_and_get instead, which takes care of reducing the
refcount on failure cases before returning from the function.
Change-Id: Ib96050d5d7ecbd717e58b8a0dde2d03312444e15
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change adds pp_tx during DMS switch for sim panel to
prevent WD timer getting updated in middle of the frame and
creating early vsync which might result in ppdone timeout.
For non-sim panels, this tx wait is not required and is
done similar to posted start.
Change-Id: Ifec68535efa19df27e651ce0a39c03627dff2089
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
At present, idle_pc_enabled flag will be set for encoders
containing only these capabilities MSM_DISPLAY_CAP_CMD_MODE
and MSM_DISPLAY_CAP_VID_MODE. When cwb is triggered,extra
power vote will be taken during kickoff and vote remains
till cwb is disabled. In between, if primary goes into idle
power collapse, vote taken by cwb will not be removed since
idle_pc_enabled flag is not set. This change updates
idle_pc_enabled flag for all encoders based on catalog
property.
Change-Id: If4f147edbd610d0302e4d6c0a3e6b7de2c729db1
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
Keep posted start as default configuration in driver
if SBLUT is supported on target.
Do not allow HAL to override driver's default frame trigger mode.
Change-Id: I46ad5c87abfb05446592b0e497a23a3a3fc62ca7
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Flush ESD status work before resetting the encoder state during
virt_disable sequence to avoid stale pointers being used in
the ESD work.
Change-Id: I4bb08a7a7ae33ad6386169667692736e554141c4
Signed-off-by: Kalyan Thota <quic_kalyant@quicinc.com>
This change allows concurrent qsync updates along with
DMS modeset condition. With this change, qsync can be
enabled or disabled in the same atomic commit along with
MSM_MODE_FLAG_SEAMLESS_DMS condition.
Change-Id: I1b51a68f947126b25a578645e92d95c9a8ae26f5
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
This change reinitializes the sde_crtc->mixers when CTL
datapath switch occurs during mode set and RM allocation
of CTL hw block is changed. This initialization is required
for CTL_LAYER programming to trigger on the new CTL allocated
from RM.
Issue case:
1. Primary Display is using CTL_0 and it is reserved.
2. Secondary Display is using CTL_1. On suspend, RM adds
CTL_1 into the free list.
3. External Display is powered on, RM allocates CTL_1 hw blk.
4. Secondary Display is powered on, RM allocated CTL_2 hw blk.
5. External Display is suspended/unplugged, RM adds CTL_1 into
the free list.
6. When any mode_set(say fps switch) occurs on secondary, RM
allocates new resources and CTL_1 is allocated.
sde_crtc->num_mixers is non zero, so all the layer programming
happens on CTL_2, but CTL_1_FLUSH bits are programmed causing
hw timeout issue.
Change-Id: I5f1f52b7673740c48b249ab4d36e80b7a1d3db96
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
This change sets CTL_UIDLE_ACTIVE register whenever uidle
is enabled and resets it only when uidle is disabled.
Change-Id: I0393d1585df4fdb79a844d04df62ac9eda949232
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
MDSS.9.0 adds support for mdp vsync based HW timestamps
on top the existing support for panel vsync based timestamps.
This allows us to enable vsync timestamp calculations for all the
use cases including a few corner cases (e.g. programmable fetch)
which we couldn't support with the existing HW.
This change adds the new HW register support and modifies the
timestamp read logic to use mdp vsync on supporting targets.
Change-Id: I2cb1b56ca9154174331c4fc1d8f82319b6989247
Signed-off-by: Michael Ru <mru@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
From Kalama, the HW scheduler abstracts the low level
PP_DONE/WB_DONE interrupts and generates a common
CTL_DONE interrupt per hw ctl. This saves the software
the irq latency delays to process the frame complete
operations when multiple encoders are involved.
If supported, this change enables and waits for the
CTL_DONE interrupt instead of PP_DONE and WB_DONE.
This change adds support to wait for CTL_DONE irq in
only command mode panels as we don't drive two WB blocks
with single CTL.
Change-Id: I084d6bfb6a9fb0b48f912fe5787401c460ec5b56
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
When downscale blur feature is enabled, calculate the mixex and crtc
width and height using the dnsc_blur's src width & height. Update the
sde_crtc_get_mixer width/height functions to return the correct size
based on the features enabled.
Change-Id: I52dd88cc52e1ca5cb37e381e92e0e3032e7b090f
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add changes to configure the downscale blur hardware block based on
the conifgs set by user-mode. Program the ctl's writeback flush and
active bits when dnsc_blur is enabled. Bind the pingpong block that
feeds pixels to dnsc_blur hw block. Disable the active bits and unbind
the pp block binding during wb disable.
Change-Id: I1961ab437e344b13d0c186c1675a5bf79b84ea74
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
The interface resolution can be different from crtc/layer-mixer WxH
when certain features like destination scaler are enabled. Use the
sde_crtc_get_width/sde_crtc_get_mixer_width functions throughout
to get the correct crtc/lm size based on different features enabled.
This will help in validating/configuring lm & plane correctly.
Change-Id: I45de5844bf7465a3389cf723479c5449a835fb0a
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Currently, writeback frame-triggers are serialized by default. Add
logic to support the different frame-trigger modes which can be set
through the connector property or encoder debugfs node.
- default: waits for frame(N-1) completion (wb-done-irq) before
configuring current frame(N) and releases the commit-thread on
frame-start (ctl-start-irq)
- posted-start: no previous frame(N-1) completion wait. Configures
frame(N) and releases the commit-thread on frame-start (ctl-start-irq)
- serialize: no previous frame(N-1) completion wait. Configures frame(N)
and releases the commit-thread on frame(N) completion (wb-done-irq)
(wb-done-irq) before configuring the next frame.
Restrict wb posted-start support only for MDSS 9.x+ targets, with older
targets defaulted to default-mode.
Change-Id: Id441378fd79ecbfcfb820da1ff23b14ccfd8e798
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Avoid drm vblank on/off for virtual displays to allow drm framework to
ignore the vblank requests. Vblanks are unnecessary for writeback as it
is triggered based on the frame-updates and not on any defined interval.
In addition, avoid vblank callback registration for concurrent writeback
encoder.
Change-Id: I205734e2e3076469dc7f775566cf5e104bac4082
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
The sde_hw_blk was meant to be a generic base object for all
SDE HW blocks, however, it enforces using a common set of ops
which is not practical when blocks have different capabilities.
Since this object was never used as intended and is not doing
anything functional today, remove the dead weight.
Change-Id: If76006c1ae5c62e8d7d77b100837dbaf6c661bd3
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
Move all the individual boolean flags from HW catalog into a
"features" bitmap. These flags are used to specify support of
various target specific features.
Change-Id: I2334b3b873f3737f91bbae4ef576408247710156
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
Currently RSC timer register programming is optimized for updating
only during timing param changes and not during RSC state changes
with same timing. Static wakeup time computation should consider
panel jitter for RSC clk state too, else it can result in RSC hang.
This change also removes extra logic for video mode prefil lines
computation for rsc config as video mode does not enable RSC solver.
Current issue scenario exposing the hang is in dual dsi display scenario
where RSC is in clock state and static wakeup time is programmed by
not considering panel jitter, after suspend/pmsuspend while waking up
if RSC switches to command state if primary enabled first and vsync
may arrive much early based on the panel jitter. RSC hw can not handle
if TE arrives earlier than static wakeup time causing RSC hang.
Change-Id: I1434fdd71eb04fdbe22b3601500493c818e9126d
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Commit b67da33a6307 ("trigger tx_wait if panel
resolution switch") increases the mode switch latency.
Alternatively, single buffer tear check registers can be
updated when vsync_in is disabled. It allows mode switch
frame trigger as posted start frame trigger.
Change-Id: I8068736b2ea01f6e4160e765fc39d7fc2a8590c9
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
