Adds ini field to control the filter for rx avg rate calculation.
0 : Filter Disabled
11000 : Max rate filter (in kbps) supported for filter
Change-Id: I6ae88b7af3d4c1fae033101e77b308949e5b3d1e
CRs-Fixed: 3628056
In the current code, RX refill buffer pool size is not initialized for
SOFTUMAC architectures, this was leading to a kernel BRK panic.
Initialize RX refill buffer pool size for SOFTUMAC architectures to fix
this.
Change-Id: I0424ba69b0d5f33386e931d4e6723fc8265e216c
CRs-Fixed: 3621417
add wlan_cfg_ctx in wlan_cfg_soc_attach for WLAN_SOFTUMAC_SUPPORT case
for compatibility with specific chipsets.
Change-Id: Icd1bbe85182d6baf1e25dceed0b45994aa9f55fc
CRs-Fixed: 3619315
add new ini to configure skb size and change it in each place its used
correspondingly
Change-Id: Id00c6351bf6bc1b9df5e19064b2057dadd315e9b
CRs-Fixed: 3584462
Currently two RXDMA_STATUS rings are allocated for the station targets
irrespective of whether DBS supported or not. Only one RXDMA_STATUS_RING
being used for non-DBS targets like QCA6750 and WCN6450, hence change
the number of RXDMA_STATUS_RING allocations to 1 for non-DBS targets.
Change-Id: I4f14c8b5cee892979765f776b37d44e99ba2d558
CRs-Fixed: 3578733
Monitor destination ring interrupt processing is configurable.
For improved CPU utilization the batch counter threshold and
timer threshold is updated and also an option is provided to make
this values configurable through INI.
Change-Id: Ibe671927f53f3e8fac7f17540c21a2c7edae427b
CRs-Fixed: 3569505
1. In lowmem profiles the number of tx_desc in 4th pool is reduced to
quarter for memory optimizations.
Added new API dp_get_updated_tx_desc which will return the desc value
from INI based on the flag DP_TX_DESC_POOL_OPTIMIZE.
2. Changes to introduce new INI to get reduced desc value for 4th tx
desc pool.
This helps optimize 0.75M per SOC in lowmem profiles.
Change-Id: I033fcaeb843019fb03bb77e0d05a3ebf60fa806a
CRs-Fixed: 3557483
TX completion ring is not configured correctly when Qdata
is enabled. This change is aimed to fix the regression.
Change-Id: Ib14a1c3a3cd57693579cedda5713eb539e853961
CRs-Fixed: 3557033
For legacy tx monitor, we need msdu completion in sequence.
Modifying the return buffer manager id during enqueue will serialize
the msdu completion.
Return buffer manager will be over ride only when tx_monitor
is turned enabled.
Change-Id: I500065077b59b3ea3561ec8fc49af8cbe58c1dfe
CRs-Fixed: 3539636
Add INI to disable AST indication. AST disable flag will be
sent to the target in resource config.
Change-Id: If30cac010681faf06bbcaa2d492d6843e3e675d0
CRs-Fixed: 3544223
Use page frag init time rx buffer allocation for efficient usage of memory.
Add ini dp_bufs_page_frag_allocs to disable and revert to original slab
nbuf allocations.
Change-Id: Iac78895addfe9da0118bc071c691a26216d6fda1
CRs-Fixed: 3553800
When the peer delete timer/vdev manager response timer expires, host checks
if the umac reset is in progress. If so, host will retrigger the timer.
It is possible that the umac reset is just completed and either of these
two timers got expired. In this case, host will assert saying that the peer
delete response/vdev manager response is not received from FW. FW may take
a few milliseconds to send the peer delete/vdev manager response to the
host after the umac recovery completes.
Hence, to avoid the crash, check if the umac reset was in progress during
the umac reset buffer window.
Add the below changes as well,
1) INI support to get the umac reset buffer window value.
2) Renamed the API dp_umac_reset_is_inprogress as
dp_get_umac_reset_in_progress_state to return either
CDP_UMAC_RESET_IN_PROGRESS or
CDP_UMAC_RESET_IN_PROGRESS_DURING_BUFFER_WINDOW.
Change-Id: Ie15ef0731bad4b0ed955a479f00e297b7ba10729
CRs-Fixed: 3522665
Add support for sw2rxdma_link_ring size cfg ini.
Also add wrapper function to get the sw2rxdma_link_ring size.
Change-Id: Ic5b17f029fe6c735785701801b75284dd489ac1e
CRs-Fixed: 3525040
Include Umac reset irq line in the mask table only
when it is enabled for 8 msi group to make sure
the legacy devices are not impacted.
Change-Id: If8f6b7f948a7c9f45247e8ff934642f0a532ff0d
CRs-Fixed: 3499500
add multiple history array to keep track of mem allocation and
deallocation for qref table.
Change-Id: I9fa97fbe5a5c36509cbb5a458851a152200318a5
CRs-Fixed: 3475981
Add new set and get APIs for cfg items so that
those cfg items can be managed from the external
components.
Change-Id: I52eb747fc6c544cfe43273c3b8b0fcc27b5a4a5f
CRs-Fixed: 3502582
As part of CPE V2 or split phy board, IPA will start using
two TX ring and for the same disable the DP interrupt mask
assignment.
Change-Id: Ia676bfa6a8b89274f5dfd313f73761132bb7909c
CRs-Fixed: 3445325
1. Add ini configuration for enabling round robin flows to
core distribution in FSE
2. Register FSE APIs to CDP FSE ops
Change-Id: Ic61c44eb9bc68a8c1a0116d4e6aa1d54cf489b62
CRs-Fixed: 3505287
Allow the ppe ds tx descriptor pool to have a maximum
size of 64k tx descriptors.
Change-Id: I4c09b6337efaabedea93f36a3477f5bdcc32f288
CRs-Fixed: 3468613
Add DP API to evaluate if TX ILP needs to be enabled,
it is only enabled if following two conditions are met,
(1) INI for TX ILP is enabled
(2) htt msdu index to qtype mapping table index 3 value is
HTT_MSDU_QTYPE_LATENCY_TOLERANT
Change-Id: I4d0c1103941b8b12b8441762dc6b45d28ee1df21
CRs-Fixed: 3447096
ppe2tcl and Umac reset interrupts need dedicated irq lines.
Hence, group some of the existing dp groups togeather
to share MSI lines to make space for ppe2tcl and Umac reset
dedicated irqs.
Change-Id: I5181caeaeb4d0107b62e7ac812c2f829fd8215a2
CRs-Fixed: 3423553
