when we enable compander for headphones, the quality
of hph playback is bad, since we have not disconnect
the right port, correct it.
Change-Id: I63ab0734870027109a7f032c47f8865083374a5b
Signed-off-by: Yuhui Zhao <quic_yuhuzhao@quicinc.com>
Optimize the init sequence for tambora, enable TXSCBIAS_CLK
and set IBIAS_LDO_DRIVER as 5ua.
Change-Id: I639b7051d03d167972f592b155072260d4e02aec
Signed-off-by: Yuhui Zhao <quic_yuhuzhao@quicinc.com>
Update the hph/ear/aux playback sequence, disable the reg
which should be disable.
Change-Id: Ib1353e686a49222f5084722cced7687815f76ab2
Signed-off-by: Yuhui Zhao <quic_yuhuzhao@quicinc.com>
Tear down the correct REQ_PS when widget power down,
that can fix the amic3 mute after ssr issue.
Change-Id: I7b5c958e79eb23184bd11375bae11dbcd51e961a
Signed-off-by: Yuhui Zhao <quic_yuhuzhao@quicinc.com>
Update the micbias enable logic for tambora,
and add some widgets to switch between amic and
va amic.
Change-Id: I2c9a7658d79a7c9d255884df7b81aa8062185d72
Signed-off-by: Yuhui Zhao <quic_yuhuzhao@quicinc.com>
Remove test reg configuration from init_reg func to
avoid pop noise in hph playback with comp enable.
Change-Id: I7c49d224e92c28cfdd2e971095ac5e6fa6db14c9
Signed-off-by: Yuhui Zhao <quic_yuhuzhao@quicinc.com>
enable swr comp port. but not set any DRE
related registers unless comp switch is
set from the mixers.
Change-Id: I57b45bb504f0851aed90521e20a94fcb359b29ff
Signed-off-by: Sarath Varma Ganapathiraju <quic_ganavarm@quicinc.com>
added 1msec delay before resetting FS cntrl, to ensure no
glitch at the start of VI feedback.
Change-Id: Ia9ae296f336e4deb4b8bedb718316a6772466a95
Signed-off-by: sarath varma ganapathiraju <quic_ganavarm@quicinc.com>
mark OTP_0 register as read register instead of read and write.
Change-Id: I666c388ba10cd00daf8ac902e0b05177503b1e26
Signed-off-by: Vangala, Amarnath <quic_avangala@quicinc.com>
System gain is miscalculated due to incorrect parsing of
device tree property. Correct the parsing logic of the
system gain device tree property.
Change-Id: I8c9c5198a139a69c2d5d9520a071123261b0581f
Signed-off-by: Phani Kumar Uppalapati <quic_phaniu@quicinc.com>
To enable datapath control for both HPH_L and HPH_R in
HPH sequencer. Which is used to fix the single channel
mute issues.
Change-Id: I1d9fb22255a2895fc2543ef5c3de02f0bdb9999d
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
Implement driver module for BT Soundwire master.
Implement support for SSR and PDR handling for BT Soundwire use case.
Change-Id: Ibc7818a08a2f65fe47311daffc03a017fbac77e3
Signed-off-by: Vangala, Amarnath <quic_avangala@quicinc.com>
Move scp1_val and scp2_val into swr_device struct and
reset this two value after ssr.
Change-Id: I549f7438f034a2de0e556bd749594fbe5db2a21e
Signed-off-by: Yuhui Zhao <quic_yuhuzhao@quicinc.com>
updated sleep time to 80us from 20us after updating the
reset gpio pin from sleep to active state to give ample time
for HW to reset the pin state to active, to resolve the
component registration issue which is seen on stability
runs.
Change-Id: Icd13bf36d56906553352e595d07e478c23d1c13d
Signed-off-by: sarath varma ganapathiraju <quic_ganavarm@quicinc.com>
Clk vote is present after teardown the usecase. which
is impacting the power, in SND_PMD call swr disconnect
to avoid clk votes.
Change-Id: I94d1ab9dc19a62132033a5715d4212dbcb7d2b0b
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
update the codec digital RX clk rate to 9P6MHZ or
11P2896MHz depends on usecase.
Change-Id: I1c7167c10ef8bcdba876be265ef90d980f822d03
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
Increase TDM interface max ch to 32 and max rate to 96kHz.
Change-Id: Icaabacff20bc08d98e0f4a6b47feaf8c09aee585
Signed-off-by: peizhong <quic_peizhong@quicinc.com>
