This change updates SSC offset value according to recent
hardware recommendation.
Change-Id: Ie822ed6ae8e383f93ca91615617dad4b4324b8a0
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Remove the CLK_GET_RATE_NOCACHE flag from all the DP and DSI
pll clocks. This will eliminate the need to recalculate the
clock rates from HW registers when querying the rates for the
PLL clocks. This will ensure that no unclocked register accesses
are done when these clocks are queried while the display core
is power collapsed.
Change-Id: Ia5e993195cadc2bced32c052bb604e9980ecd4d8
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
In continuous splash use cases, the display is enabled in
the boot-loader. During display kernel probe, to enable clocks,
the rate is calculated by reading the hardware registers before
the corresponding software rate is set. At times when these rates
are nearly equal, the call for set rate never happens. This can
cause abnormal behavior. In this change during hand-off we don't
recalculate the clock rate to ensure the software programs the clock
registers accordingly.
Change-Id: I421c523ffd48a0cb73d7721c6d74c8e68aa6d9a5
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change brings msm display driver including sde,
dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel
project. It is first source code snapshot from base kernel project.
Change-Id: Iec864c064ce5ea04e170f24414c728684002f284
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
