Commit Graph

16 Commits

Author SHA1 Message Date
Rajkumar Subbiah
c0d4857a81 disp: msm: sde: adjust intf timing for widebus
From Lahaina onwards, widebus is enabled for compressed DSI stream.
This change adjusts interface timing parameters to account for widebus.

Change-Id: Ie6b739ed2cdb515064e3a94404b3e0fe07755d7e
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
2020-04-09 14:14:55 -04:00
Jayaprakash
4536e7b2a6 disp: msm: sde: add null pointer checks
Add null check for pingpong block used during
the commit phase.

Change-Id: I3ebbcfe9c42ee6d1201a141f553bbb0a0ae97ad6
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2020-03-29 09:51:30 -07:00
qctecmdr
1fc486ad3e Merge "disp: msm: sde: ctl hw flush ops clean up" 2020-03-21 13:08:07 -07:00
Narendra Muppalla
68ee65353b disp: msm: sde: align timing engine vsync based on panel vsync
This change adds logic to align timing engine vsync with panel
tear check if it is supported.

Change-Id: I3f881f392929589848c893f567822b21c0650000
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2020-03-11 10:14:57 -07:00
Dhaval Patel
9438f3448b disp: msm: sde: add underrun line count information
Add underrun line count information for each underrun.

Change-Id: I34a740c33240fa8d444f4bbc3b8b014b0282fca1
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2020-02-28 11:57:47 -08:00
Nilaan Gunabalachandran
f51424f8a7 disp: msm: sde: ctl hw flush ops clean up
Using individual flush functions for each active hw blk
is not scable-able for future use. Clean up the ops to merge
all flush functions into one and manage HW block id
with same API.

Change-Id: I62afbc51fa7d345b3a1f5721e5e09661a4215f7a
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-02-25 14:18:59 -05:00
Abhijit Kulkarni
7317dc417f disp: msm: sde: intf accept 64-bit compressed pixels
This change enables the interface hw block to accept
64-bit compressed pixels. This configuration is enabled based
on hw capability. For current hw, this is required any time
the compressed pixels flow through the interface block,
whereas in the previous version of DPU hw this configuration
is only required for topology using 4 way dsc merge.

Change-Id: I7bf79d035dba5084c5057022a7fa1117479e8d52
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-29 22:39:44 -08:00
Abhinav Kumar
e3f23771ba disp: msm: add support for variable compression ratios
Currently the compression ratio is hard-coded to either 2:1 or
3:1 in several places. This is not sufficient for new compression
algorithms as they can support higher compression ratios.

Add support for calculating the compression ratios from the source
and target bpp thereby eliminating hard-coding.

Change-Id: I6383f3d0c781193d0a9ed74df5a95d8e856edb3d
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
2020-01-29 13:46:57 -08:00
Abhinav Kumar
27844b7b60 disp: msm: dp: remove usage of compression ratio enum from DP driver
As overall display driver is moving away from hard-coded compression
ratios, prepare the DP driver for the same by removing the usage of
the compression ratio enum.

Change-Id: I298db7d20baed8afec9f96dff8c7e950702bfec9
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
2020-01-29 13:46:46 -08:00
Abhinav Kumar
c4f5050e13 disp: msm: add VDC topology related changes
Add support to configure the DPU pipeline to support VDC-m
topologies.

Change-Id: Ib8ce9a0eaeaa838759fb09cb2ee164d4765e4989
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
2020-01-29 13:45:35 -08:00
Jayaprakash
aad3dd4525 disp: msm: sde: update avr mode config during commit prepare
Add changes to support avr mode config update during
prepare commit which happens before gpu fence wait
for the input buffers.

Change-Id: Ib2cb5b7e1f10501914c003f6cf066b85048f79d4
Signed-off-by: Kalyan Thota <kalyant@codeaurora.org>
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2019-10-18 12:53:56 +05:30
Jayaprakash
ad40a300a1 disp: msm: sde: allow qsync support along with VRR
Allow Qsync and VRR features to be supported independently
by display driver. Restrict the feature availability in
same composition cycle.

Change-Id: I696eb72a2b4f9451e142ffdc5acccc8987c36b6d
Signed-off-by: Kalyan Thota <kalyant@codeaurora.org>
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2019-10-17 17:07:33 +05:30
Dhaval Patel
6f06e5cd6f disp: msm: sde: wait for specific pp_done instead of zero
2 Frames transfer pending is possible with posted start.
One ongoing frame and another triggered frame. Current SW
waits for pp_done interrupt if pending frame count is greater
than 1. It is possible that interrupt may be missed for ongoing
frame. In that case, SW should run pp_done wait for one by one
frame instead of two frames together. It allows encoder to
check the ctl scheduler status and trigger the frame done
event on time.

Change-Id: I4817842292d96747890ee70da8a5bdf9b56816ed
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2019-08-20 21:12:52 -07:00
Nilaan Gunabalachandran
c6092f3e66 disp: msm: sde: log intf framecount in event logs
Log hardware interface framecount during te and vblank irqs for
command and video mode panels, respectively. This will help in
debugging any missed frames.

Change-Id: Ie86f686c4cc12de6a1f31aa47d4c7a5b8a68ea55
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2019-06-26 11:54:51 -04:00
Samantha Tran
1ab07a4d7c disp: msm: add changes missing during snapshots
This change ports the missing changes from 4.14 to 4.19
that were missed. It includes changes up until
commit 0f8fb25421ff ("cnss2: Add device version to
SOC info structure").

Change-Id: Idfdfe891f146e389e3c65cc3fc4c98d93220e789
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2019-06-03 09:07:38 -07:00
Narendra Muppalla
3709853456 Display drivers kernel project initial snapshot
This change brings msm display driver including sde,
dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel
project. It is first source code snapshot from base kernel project.

Change-Id: Iec864c064ce5ea04e170f24414c728684002f284
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2019-04-14 22:20:59 -07:00