introduced core error state and added changes
to refine core state machine.
Change-Id: Ib3b94fd3798e902b7a6cfc5de45820558c89806e
Signed-off-by: Govindaraj Rajagopal <quic_grajagop@quicinc.com>
Poll for AON spare register BIT(0) to become zero before
asserting XO reset from video driver to ensure CVP/EVA driver
is not asserting XO reset around the same time. Asserting
XO reset by both driver at the same time may result in
unpredictable behavior.
Change-Id: I71a0bd0175ef7701c9a855abbf3c2e741d937dfb
Signed-off-by: Maheshwar Ajja <quic_majja@quicinc.com>
Remove addtional mvs0c clock reset which is not
required from power off sequence
Change-Id: I2077cb0ceee6451cd2d2af067ac8a7be3335dd16
Signed-off-by: Deepa Guthyappa Madivalara <quic_dmadival@quicinc.com>
Introduce core->sub_state similar to inst->sub_state.
[1] pm_suspended - moved to this substate in case of PM suspend
[2] handoff - moved to this state after successful
handoff_regulator call.
[3] fw_power_control - moved to this state in case of IFPC.
[4] power_enable - will track core power_on/power_off status.
[5] page_fault - used to rate_limit fault logs.
[6] cpu_wd - indicates hw fired wd interrupt.
[7] video_unresponsive - moved to this state if sync cmd fails.
Change-Id: Iceb65cf404fd93aff7846860b0276307e4eab570
Signed-off-by: Govindaraj Rajagopal <quic_grajagop@quicinc.com>
Move adjust/set control functions to common/platform.c as part of
upstream effort.
This is part 1 of the change.
Change-Id: I8c440740fe785b5b052c4d44963ea34c21419fa4
Signed-off-by: Ankush Mitra <quic_ankumitr@quicinc.com>
Add assert and deassert axi and mvs0c resets to
avoid video hardware unresponsive issues due to
multiple power collapse sequence execution.
Change-Id: I25ec99eab6b50111161ec9486ea1155bee63f7fc
Signed-off-by: Maheshwar Ajja <quic_majja@quicinc.com>
- Add assert and deassert reset control functions to
update power off sequence in pineapple chipset
- Rename clock names to match with clock macros
Change-Id: Ic6dc0daac8110597bfcb02cceba94d2b97548723
Signed-off-by: Maheshwar Ajja <quic_majja@quicinc.com>
1. Allow turbo for HEVC 10bit all intra decoding;
2. Add 25 percent extra to VSP cycle for HEVC
10bit all intra decoding;
Change-Id: I794b2a896f7e9444c8979abdb15b8e673a5270ee
Signed-off-by: Zhongbo Shi <quic_zhongbos@quicinc.com>
Signed-off-by: Ankush Mitra <quic_ankumitr@quicinc.com>
if PC fails for 10 times then video driver is treating that situation
as fatal and doing force core_deinit(), in this case firmware will not
follow vcodec power_collapse sequence and if there any pending
transaction from any session it will cause smmu_fault during next
firmware_boot sequence. Added change to perform vcodec power_collapse
from power_off_iris3_hardware() incase of core_deinit due to PC failure.
Change-Id: I45e32985d87b5cc882c4f96f77d1cabc796e6ba0
Signed-off-by: Govindaraj Rajagopal <quic_grajagop@quicinc.com>
Signed-off-by: Ankush Mitra <quic_ankumitr@quicinc.com>
Added call_res_op() macro and used at all possible
places to avoid invalid pointer dereference issue.
Also added changes to cleanup unused functions.
Change-Id: Id77711ad9eaf7b407208567b0fde1f2693588641
Signed-off-by: Govindaraj Rajagopal <quic_grajagop@quicinc.com>
1. Update core power down sequence.
2. Update hw power up sequence.
Change-Id: I428869ac92154b23cdbe3f51c7b299fe8a6cc71b
Signed-off-by: Chinmay Sawarkar <quic_chinmays@quicinc.com>
