To avoid confusion in code reading and prepare for
future compatibility changes.
Change-Id: I43d61e18d2e2d75d1fd46ceb2e763511329ee32d
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
For FW to hold debug info. Simplify driver structure for easy
dump in T32.
Change-Id: Ib310a3d9fe3437d5ce49783eb813fbb2d8bd3216
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
Recovery mechanism is added to invoke SSR when WD ISR is triggered.
Change-Id: I6f7a289f822c6f1a50494cd6a4855a2c3ba2cc72
Signed-off-by: Palak Joshi <quic_palakash@quicinc.com>
Non-secure ARP and CRC in BUFFER_TYPE, enabling IFPC.
Change-Id: I551e29e7770cdfd83b0ed9f7f925fb8bd6e6a4a6
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
propagated sync v2 support from 2.0
reference 4162025
Change-Id: I3427657e21e7eda92088d828203a330ba3c86335
Signed-off-by: Yu SI <quic_ysi@quicinc.com>
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
The change also allows runtime change of auto-pil setting. It will
help presilicon bring up.
Change-Id: I9fd97a09e6730a2e13ae4503c74f8a2962c614c5
Signed-off-by: George Shen <quic_sqiao@quicinc.com>
merged tip source code from eva-kernel.lnx.1.0,
and verify the promotion flow.
Change-Id: I031508fd8a23995a166506f3d190e5e228eb13c2
Signed-off-by: Yu SI <ysi@codeaurora.org>
Enabled FW static dump.
Enabled VA_MD for CMD and MSG queues, both for CPU and DSP.
Enabled VA_MD for debug structs.
Change-Id: I9a5a2418620cd0608b90301eefe0726a462c1ce3
Signed-off-by: Aniruddh Sharma <anirshar@codeaurora.org>
For better debugging, it's conveninet to stall device when
EVA SSR happens.
Change-Id: I1bfd97d99ad3b6c0276282be9de4e7bb2456227d
Signed-off-by: George Shen <sqiao@codeaurora.org>
Support configurable number of SSR tolerance before calling
BUG_ON in SMMU fault scenario.
Change-Id: I19dabbeaa1cf5be86f42a6ace62ef5da12743e79
Signed-off-by: George Shen <sqiao@codeaurora.org>
Avoid deadlock in DSP EVA session creation after EVA SSR.
Change-Id: I22b363883db5d3bf8e8554a3708cb549437899ba
Signed-off-by: George Shen <sqiao@codeaurora.org>
Add debug option using debugfs to disable DCVS.
Add extra check for DCVS.
Change-Id: I989ef72857dde306fa0ca9466843ebc1d2b30f85
Signed-off-by: Ronald Karyodisa <ronaldk@codeaurora.org>
integrated mmrm api
added make file and kbuild support
code ready, enable flow.
Change-Id: Ic7da142bc68e60312ee9a12128847be8ed27a685
Signed-off-by: Yu SI <ysi@codeaurora.org>
EVA control is allowed to power collapse EVA core during inter
frame idle time.
Change-Id: I4da4efe9a5d8f2c9a5f9dba6286cbd6c5a8ab903
Signed-off-by: George Shen <sqiao@codeaurora.org>
Update EVA CC register offset and disable power collapse.
Change-Id: I142053666e80c24ce1b12a4566b28638c615ec9b
Signed-off-by: George Shen <sqiao@codeaurora.org>
Enable auto pil and all debug loggings for bring up.
Change-Id: I14e56e0f13269db78ef9a8e6bc63619d90dd62bc
Signed-off-by: George Shen <sqiao@codeaurora.org>
