On Lahaina platform it is seen that WBM IDLE ring init is failing,
Write to WBM_IDLE link ring LSB write is failing.
Add temporary WAR to do back to back write of WBM IDLE link ring
LSB address config register.
Change-Id: If0c20da06bafa3037845e9806934f9e4dfbd1c1c
CRs-Fixed: 2690495
MPDU start TLV structure is different across pine and hk/cyp. The
access to individual members of this structure is already taken care
in HAL APIs.
Tha addition of offset is redundant and wrongly defined offset values
led to wrong interpretation of mpdu start tlv fields like RSSI in
QCN9000.
Change-Id: I3c0daa1c9117eecd1566a1d52d794e92dc292fa4
CRs-Fixed: 2682570
make sure both PCIe and device are force woken for the register
writes for hsp, or write may fail.
Earlier WAR is not required as we have root caused it.
Change-Id: I350b810a6cef8eec46428e57f5b779f888552c1b
CRs-Fixed: 2677342
rts full destination address is needed to be able to do check on mac
to be able to recreate cts frame correspondingly.
Change-Id: I3ec7e765bb4a0645a1495b4ca42d81fd3134cc5d
Currently, mcopy mode delivers first msdu(fcs_passed 128 bytes) per-ppdu
to upper layer, add support for Extended mcopy mode to deliver first
msdu(128 bytes) per-MPDU(fcs_passed).
Change-Id: Ib345fc14a8d468788b9de78516d27e8dff24caa4
CRs-Fixed: 2644175
Size of the TLVs have changed across generation of chipsets
Offset values need to be configured into DMA register for preheader DMA
Added APIs to get offsets of each TLV based on chip type
Change-Id: Ic011332cbf3a1017f324f246e47c9e2c91441c70
On Lahaina platform it is seen that WBM IDLE ring init is failing,
Write to WBM_IDLE link ring LSB write is failing.
Add temporary WAR to do back to back write of WBM IDLE link ring
LSB address config register.
Change-Id: I7f72abb7226e1d7beee127ebda88488172147f21
CRs-Fixed: 2647762
Enable SW2TCL_CMD ring for data on QCN9000, QCA8074 V2/V1
and IPQ6018 targets.
Enabled 4th Tx ring for data enqueue to HW.
Transmit completions for packets from CPU0 and CPU3 are routed to
WBM2SW Completion ring 2.
WB2SW completion ring2 is mapped to CPU3.
Change-Id: Ied4c4704e1f8623e909ad45c547a611de26c7ec5
Function added to convert given channel number to correct
channel frequency using the Channel center frequency and
populate it correctly inside the radiotap header
Change-Id: Iea2a9ee7d496b2aa0dbf8d6741a32d2dbfa3503d
CRs-fixed: 2637424
The HE GI and HE LTF values are obtained from phy
TLVs in monitor path. The stats used in host have an
enum defined used by other upper layer code.
The radiotap spec defines different set of enums.
Add translation function to convert host stats enum
to radiotap defined enum for sniffer capture purpose.
Change-Id: I8c76adb42b0623e83958f7a37147b74e72b1ce74
CRs-Fixed: 2636051
Support RX 2K jump/OOR frame handling from REO2TCL ring.
(a) configure REO error destination ring register to route 2K jump
/OOR frame to REO2TCL ring.
(b) for 2K jump RX frame, only accept ARP frame and drop others,
meanwhile, send delba action frame to remote peer once receive first
2K jump data.
(c) for OOR RX frame, accept ARP/EAPOL/DHCP/IPV6_DHCP frame, otherwise
drop it.
Change-Id: I7cb33279a8ba543686da4eba547e40f86813e057
CRs-Fixed: 2631949
Initial changes for ipq5018 compilation.
Added device ID and target type checks for ipq5018 traget.
Change-Id: Ib86a371fbe66749fcb6d114e7a4a9931b684e03d
Rather than extracting msdu end pkt tlv information per field basis
during fast data path, extract msdu end pkt tlv information at once
and store in local structure.
Change-Id: I0877ba4f824d480cc0851c72090f010852d0d203
fix the issue for block ack/ack for tx capture mode.
1. Hanndle BAR frame.
2. set rate for ACK frame.
3. Check block ack session and use block ack if block
ack session is established.
4. no ACK for broadcast probe request.
5. not ack if the ack policy is set to no ack in qos control.
Change-Id: I4f22c1c976334978fb971b42319fb3a6e43a00c2
Add monitor mode support to capture packets over 6GHz frequencies by
getting capture frequency from pdev.
Change freq type to qdf_freq_t.
Change-Id: I7b6edc43e254dc98a3c2939c369874bec9d16ddd
CRs-Fixed: 2568970
the current HAL API is to read the WBM internal error
bit from the wbm release ring descriptor is always taking
HKv1 HW structure. But the wbm_internal_error bit
placement has changed from HKv2, for this reason we have
to use target specific HAL API.
Change-Id: I44789180754ca21ae59650b6d8620321a1f12569
Channel Frequency Response(CFR) feature requires PPDU information
for correlation with CFR data. Host subscribes for the relevant PPDU
status TLVs via the Host RX monitor status ring. During monitor status
ring reap, all information needed for CFR correlation is accumulated
in a HAL PPDU structure and delivered to WDI event subscribers.
Change-Id: I3662b60375cb8886447a2fba3efead6a1ef3a98d
CRs-Fixed: 2593408
sw_frame_group_id decides process for frame. USER_STATS tlv case uses
sw_frame_group_id to add qos_null frame control to rx_status.
Change-Id: Ia3da8dbe4fc4c2d0f21fa8864e6b4e87170ba8f6
The reo destination ctrl registers
HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR and
HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR are used for mapping
msdu packets to different reo rings.
For QCA6390,
reo remap values varied from 0 - 7 so every 3 bits in
the register were used to map to a particular reo ring.
For QCA6490,
reo remap values vary from 0 - 9 as two extra reo rings are
added so we are using 4 bits in the register to map to a
particular reo ring.
Use the macros directly provided in the header files
to map reo rings.
Change-Id: I6d64266d3b388b3453b7df959048e3d693cf0a40
CRs-Fixed: 2544102
Add the following support for QCA6490:
1. Initialize the qca6490_hal_hw_txrx_ops
2. Initialize the hw_srng_table
3. Attach hal_qca6490_attach
Change-Id: Ic53c520ef804eb4fbe1434c704e9040c83011d3d
CRs-Fixed: 2522133
Implement hal_rx_msdu_get_flow_params API
per chipset as the macro
to retrieve the flow parameters is
chipset dependent.
Change-Id: I6ef83232ebdf7497871a7fc588e082d14cdc9e75
CRs-Fixed: 2522133
Add the following macros:
1. HAL_REO_CONFIG
2. HAL_RX_MSDU_DESC_INFO_GET
3. HAL_RX_LINK_DESC_MSDU0_PTR
Add the relevant function pointers to
retrieve the descriptor info from the
above mentioned macros based on a
given chipset.
Change-Id: If44ae3d91397f1b1b0c36a49ce56a2c5e719434e
CRs-Fixed: 2522133
Add the following macros:
1. HAL_RX_GET_FC_VALID
2. HAL_RX_GET_TO_DS_FLAG
3. HAL_RX_GET_MAC_ADDR2_VALID
4. HAL_RX_GET_FILTER_CATEGORY
5. HAL_RX_GET_PPDU_ID
Also add function pointers to
retrieve the flags from the above
macros.
Change-Id: I334b198588ceba77cd30bdde7ebc500cdbe18358
CRs-Fixed: 2522133
Implement hal_reo_status_get_header_generic
based on the chipset as the macro to retrieve
reo_status value is chipset dependent.
Change-Id: I43bd624bec37fb051f33b4828fcf7cd3e4b2a61e
CRs-Fixed: 2522133
Implement hal_rx_get_rx_fragment_number
based on the chipset as the macro
HAL_RX_MPDU_GET_SEQUENCE_NUMBER is
chipset specific.
Change-Id: I967190fa3a55d45f46760f58eab5007bf5fa908f
CRs-Fixed: 2522133
1. Assign correct first msdu payload
2. Reset mpdu fcs ok bitmap upon reception of next ppdu
3. Free rx_ppdu_buf_q in error cases
Change-Id: I4f2e687d51d1e10693adc9cfcdee49190ba6815c
CRs-Fixed: 2502889
Add device ID change and target type checks for pine.
Also remove memory war added for Hk emulation.
Change-Id: Idf531a48a03202d4fb241a92a1d671ee2b94cfbd
CRs-fixed: 2453899
Read extra bits of fcs okay bit map from
RX_PPDU_END_USER_STATS_EXT TLV and use the same
to send first fcs okay packet in case of M COPY
CRs-Fixed: 2499150
Change-Id: I1a25971ea789dd7fddddb312af8a18a4cccdc178
Tags are programmed using wlanconfig commands. Rx IPv4/v6
TCP/UDP packets matching a 5-tuple are tagged using HawkeyeV2 hardware.
Tags are populated in the skb->cb in the REO/exception/monitor data
path and sent to upper stack
CRs-Fixed: 2502311
Change-Id: I7c999e75fab43b6ecb6f9d9fd4b0351f0b9cfda8
Add code to replace usage of void pointers from
HAL layer and instead use appropriate opaque pointers
Change-Id: Id950bd9130a99014305738937aed736cf0144aca
CRs-Fixed: 2487250
Add code to remove void pointer usage for hal_srng
and use opaque pointer dp_hal_ring_t instead.
Change-Id: I6907f7376d7fe3c9180b8795bd96f49fead2ec64
CRs-Fixed: 2484404
Add code to remove void pointer usage for hal_soc
and introduce opaque pointer to be used intead of void
from dp layer into hal layer
Change-Id: Ia38571174c6ed79558d0f0c9cd1a0f4afaa66483
CRs-Fixed: 2480857
Filter fcs_err frames and pass only first fcs ok msdu payload
from ppdu to upper layer
Change-Id: Ibf739193275f4f5a5c3e786abbbaa45165b5aa13
CRs-Fixed: 2439392
Add max user_id check while accessing ppdu_info->rx_msdu_info[]
to avoid out of bound array access
Change-Id: Ifcc298d1fd8bd00db5eb2d1777a7ff5af894afe6
CRs-fixed: 2477005
A random crash may be caused by out of range access. Add MU
user id check to prevent out of range access.
Change-Id: I531d6c03024c4a6af4e0db97ea00d0874aaef387
The current calculation of head/tail pointer for
srng gives an index in the array by skipping
entry_size dwords.
The head/tail pointers are preffered to be the
index values like in the srng registers, which
brings them in alignment with the other usage of
head/tail pointers.
Fix the calculation of head/tail pointers for srng
by avoiding the division by srng entry size.
CRs-Fixed: 2469332
Change-Id: If9a167f3fac3cb39ebe59618e9ad2224d9e54bcc
