Commit Graph

2781 Commits

Author SHA1 Message Date
Veera Sundaram Sankaran
825bb55976 disp: msm: sde: add system cache support for writeback
Add support to enable writeback block to use system cache for writing
the output buffer. This is useful in cases where output is routed to
primary source pipes with 2-pass composition. The implementation is
modelled based on existing pipe based cache configuration.

Change-Id: I2b9a96c5b42eb5727d11ca0f337aeeb4e69362c9
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-11-17 14:57:02 -08:00
Veera Sundaram Sankaran
5464d726ba disp: msm: sde: avoid pp-done wait during autorefresh disable case
From MDSS 9.x, the pp-done wait requirement as part of autorefresh
sequence is not required. Add a catalog flag to avoid the wait for
mdss 9.x+ and to support backward compatibility.

Change-Id: Ieca008d3d6ef0f7326b65433ef42ed9f49a94f87
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-11-17 14:56:26 -08:00
Veera Sundaram Sankaran
76e7c6acd3 disp: msm: sde: use crtc_width instead of hdisplay for crtc/lm
The interface resolution can be different from crtc/layer-mixer WxH
when certain features like destination scaler are enabled. Use the
sde_crtc_get_width/sde_crtc_get_mixer_width functions throughout
to get the correct crtc/lm size based on different features enabled.
This will help in validating/configuring lm & plane correctly.

Change-Id: I45de5844bf7465a3389cf723479c5449a835fb0a
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-11-17 14:56:19 -08:00
Veera Sundaram Sankaran
e1c71c86e5 disp: msm: sde: add ubwc error status for writeback
Add support to read and clear the ubwc error status for wirteback.
Log the status during writeback timeout cases to help in debugging.

Change-Id: I11f3827d4a88565b81b21b651971cec55ba06298
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-11-17 14:56:11 -08:00
Veera Sundaram Sankaran
762252400d disp: msm: sde: expose early-wb-fence option for 2-pass composition
Add a writeback connector property EARLY-FENCE-LINE to give usermode
the control on when to trigger the retire fence. This option is useful
in 2-pass composition, where the writeback triggers the retire-fence
early based on the prog-line which allows primary to start the fetch
before wb transaction is fully completed. This helps to keep the clks
and bw low. WB hardware generates the line-ptr-irq when wb output reaches
the configured prog-line. Retire fence is triggered based on the irq by
default and wb-done handles for cases where line-ptr-irq is missed.

Change-Id: I20867979693dc3447f77da24cd7e88305947fb6d
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-11-17 14:56:03 -08:00
Veera Sundaram Sankaran
95300ca3df disp: msm: sde: add programmable lineptr support for writeback
From MDSS 9.0, writeback supports a programmable lineptr support, which
generates an interrupt when the configured writeback output height is
reached. Add software support to configure the prog_line and to process
the interrupt.

Change-Id: I3293ad2984c51417e4691c5b11e9c9a010067e1c
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-11-17 14:55:46 -08:00
Veera Sundaram Sankaran
0cf7ba9a4a disp: msm: sde: add all frame-trigger modes support for writeback
Currently, writeback frame-triggers are serialized by default. Add
logic to support the different frame-trigger modes which can be set
through the connector property or encoder debugfs node.

- default: waits for frame(N-1) completion (wb-done-irq) before
  configuring current frame(N) and releases the commit-thread on
  frame-start (ctl-start-irq)
- posted-start: no previous frame(N-1) completion wait. Configures
  frame(N) and releases the commit-thread on frame-start (ctl-start-irq)
- serialize: no previous frame(N-1) completion wait. Configures frame(N)
  and releases the commit-thread on frame(N) completion (wb-done-irq)
  (wb-done-irq) before configuring the next frame.

Restrict wb posted-start support only for MDSS 9.x+ targets, with older
targets defaulted to default-mode.

Change-Id: Id441378fd79ecbfcfb820da1ff23b14ccfd8e798
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-11-17 14:54:41 -08:00
Veera Sundaram Sankaran
5a1c44d2e2 disp: msm: sde: add ctl-start interrupt support for writeback
Add ctl-start-irq support which serves as an indication the
HW read the current frame's configuration and software is free
to program the next frame.

Change-Id: I9f6b180cf9e47894ca81d2d4b6ac724827d1368c
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-11-17 14:54:33 -08:00
Veera Sundaram Sankaran
eeb66b8516 disp: msm: sde: wait for tx-done during cwb disable
Currently, cwb disable path issues a cleanup flush & waits for the
commit-done. Wait for the tx-done to ensure the transfer is complete.

Change-Id: I509711c157f1d6646646ad96ed140d6bc76d2dba
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-11-17 14:54:25 -08:00
Veera Sundaram Sankaran
30d5ac5184 disp: msm: sde: remove vblank support for writeback
Avoid drm vblank on/off for virtual displays to allow drm framework to
ignore the vblank requests. Vblanks are unnecessary for writeback as it
is triggered based on the frame-updates and not on any defined interval.
In addition, avoid vblank callback registration for concurrent writeback
encoder.

Change-Id: I205734e2e3076469dc7f775566cf5e104bac4082
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-11-17 14:54:18 -08:00
Veera Sundaram Sankaran
1428cbb7d0 disp: msm: sde: remove unnecessary wb feature flags & reg-offset
Remove the hw feature flags that are set by default for writeback as
it does not add any value. As part of the change, remove the unused
wb register offsets.

Change-Id: I04376242e764d8d0a1edb763c9f799d7ae5447ac
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-11-17 14:54:10 -08:00
Veera Sundaram Sankaran
f57c003810 disp: msm: sde: remove wb kickoff/frame count & bypass_irqreg logic
Remove the writeback kickoff_count/frame_count & start/end time
logging. These are redundant counters used for debug purpose. The
pending_retire_fence_cnt and event-logs timestamp can be used for
this purpose. Remove the bypass_irqreg flag as well as its not used.

Change-Id: I1644325afc214f75c76baad615da90c8114836cc
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-11-17 14:54:03 -08:00
Amine Najahi
d36499ca86 disp: msm: sde: add support for DMA 4,5 for Kalama
Expand various SSPP and CTL related data structures
to support DMA 4,5.

Change-Id: I0ce052b6a2f1599a9b6eb82ce8e4f34f4c68333d
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2021-11-17 17:12:31 -05:00
Amine Najahi
2d3a255c06 disp: msm: sde: enable VBIF clock split feature for Kalama
Enable VBIF clock split feature in catalog for Kalama target.

Change-Id: I84b92764b62012955ae153e228b890bacfe1587e
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2021-11-17 13:31:05 -05:00
Amine Najahi
c8a4cdc761 disp: msm: sde: add support for WB VBIF clock split
Add support for localized CLK_CTRL access through WB
hardware block.

Change-Id: I408d1bbc798902d1abc7da5bcae9492baa3159c8
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2021-11-17 13:30:55 -05:00
Amine Najahi
c526f4aefa disp: msm: sde: add support for SSPP VBIF clock split
Add support for localized CLK_CTRL access through SSPP
hardware block.

Change-Id: I86345c94cb12c5584337aa45b562bceaab6cf8e6
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2021-11-17 13:25:21 -05:00
Amine Najahi
ca4acd5270 disp: msm: sde: add support for split VBIF clock access
From Kalama onwards, the VBIF CLK_CTRL register has been moved from TOP block
to individual hardware block memory range.

This change is adding a backward compatible solution to support
per block VBIF CLK_CTRL access by allowing each HW block to register
set of callback ops. Additionally, it adds DMA and IPCC/MSI VBIF CLK_CTRL
block type.

Change-Id: Ia82ced34cfa1636b57cd1c03b327faf923be482a
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2021-11-17 13:22:22 -05:00
qctecmdr
80a394d31a Merge "disp: msm: sde: update uidle_db_updates in both enable/disable cases" 2021-11-17 01:00:40 -08:00
qctecmdr
af3b57299d Merge "disp: msm: sde: fix traffic shaper prefill calculations" 2021-11-17 01:00:40 -08:00
qctecmdr
2eaf8739f0 Merge "disp: msm: enable dsc support for 422 with 10bpc and 8bpp" 2021-11-16 14:01:20 -08:00
Raviteja Tamatam
d098764f5b disp: msm: sde: update uidle_db_updates in both enable/disable cases
uidle_db_updates are generated when CTL_x_UIDLE_ACTIVE is set to 1.
It needs to enabled in both uidle enable and disable cases.
CTL_x_UIDLE_ACTIVE is set to 0 only in cases where uidle configuration
is not updated.

Change-Id: If7655e4eae351bac248f0906c473cdfaf93f2b8a
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-11-15 13:12:58 -08:00
Manaf Meethalavalappu Pallikunhi
479a5292e6 disp: msm: limit display brightness max cooling device level
Based on panel hardware support, display brightness levels can
be very high value. This high value display brightness cooling
device levels can cause exceeding PAGE_SIZE for cooling device stat
buffer. It leads to buffer failure for cooling device stat feature.

Limit display panel mitigation level max to 255. If hardware
supports more than 255, then scale brightness levels fit
into above limit.

Change-Id: Ieeee4ff2aa5cd884819b30b4fd9839e48ac4d804
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
2021-11-15 05:25:37 -08:00
qctecmdr
61963b0791 Merge "disp: msm: update rsc vsync timeout value dynamic" 2021-11-14 06:03:48 -08:00
qctecmdr
195baab07b Merge "disp: msm: sde: add check for sunlight visibility scale" 2021-11-14 06:03:48 -08:00
Prabhanjan Kandula
8bccb3e212 disp: msm: enable dsc support for 422 with 10bpc and 8bpp
Add DSCv1.2 native 422 format with 10bpc and 8bpp config
and format specific fixed rate control parameter table
entries as per the systems recommended settings.

Change-Id: Ibd1a5203be2c59f4699537a31f9ae6d69bcfe5ab
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
2021-11-11 16:36:55 -08:00
qctecmdr
99f4b07f1d Merge "disp: msm: sde: send event on trusted vm transition" 2021-11-11 14:24:25 -08:00
qctecmdr
6aeec823b3 Merge "disp: msm: dp: clear all dp interrupts before deinit" 2021-11-11 14:24:25 -08:00
Narendra Muppalla
6e7a48579b disp: msm: sde: enable ctl path and irqs for wb1
This change enables support for wb1 in ctl path and
adds irq support.

Change-Id: Iebbe35725aa279b8e02217ea93ba1b481f5e869f
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2021-11-11 13:16:03 -08:00
qctecmdr
b5da8ebb6a Merge "disp: msm: dp: check for active panels ptr before cleanup" 2021-11-11 10:12:37 -08:00
qctecmdr
d0b2b45c89 Merge "disp: msm: dp: reduce hdcp error level for inactive state" 2021-11-11 10:12:37 -08:00
Yashwanth
a5382aff7e disp: msm: sde: deprecate idle notify work scheduling
This change deprecates idle notify work for video mode
since idle timer will be maintained by userspace.
As part of idle notify work, syscache state is changed from
CACHE_STATE_NORMAL to CACHE_STATE_PRE_CACHE along with
notifying to the userspace. This change removes
CACHE_STATE_PRE_CACHE in the state machine and state is
updated from CACHE_STATE_NORMAL to CACHE_STATE_FRAME_WRITE
whenever the cache property is set.

Change-Id: If3b2c34be954cb625aca76da81fd854c077a8250
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-11-11 11:07:54 +05:30
Rajkumar Subbiah
29534b6d5c disp: msm: dp: clear all dp interrupts before deinit
If there are any uncleared DP interrupts before deinitialing
and turning off the clocks, the interrupt might get stuck at
the MDP level and can't be cleared without turning the DP
clocks back on. To avoid this situation, this change clears
all the interrupts before turning off the clocks.

Change-Id: Id13b102fa81c85f92ae8c1d11ffaf7d5bad5fd12
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
2021-11-10 17:46:31 -05:00
Ping Li
dd2e1fd03f disp: msm: sde: add check for sunlight visibility scale
Add check to clip the sunlight visibility scale to an upper limit of
MAX_SV_BL_SCALE_LEVEL * 4.

Change-Id: I8cc7bf8fba90e115d046ec030983801ce6d93c1d
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Yuchao Ma <yuchaom@codeaurora.org>
2021-11-10 09:43:35 -08:00
Rajkumar Subbiah
6c8c95f99e disp: msm: dp: add qos vote during hdcp authentication
HDCP authentication has strict timing requirements and if the
display is on static screen during this time, it is possible
that SDE removes the QOS vote when it detects static display,
thereby affecting the hdcp authentication process.

This change adds qos support in dp driver to vote exclusively
for DP. If valid QOS settings are provided in dtsi, then the
driver adds the vote when it starts authentication and removes
the vote when authentication is completed.

Change-Id: I1d8bc098d0857b13fdf1ca089b6dd2d3f381bdb8
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
2021-11-09 16:56:58 -05:00
Sandeep Gangadharaiah
1025b3c40a disp: msm: dp: reduce hdcp error level for inactive state
During an HPD, HDCP IRQ handler prints error log and exit
if HDCP state is inactive or authentication failure.
Inactive state is a benign error and auth failure will be
reported by hdcp kernel module. This change will downgrade
this error log to debug log.

Change-Id: I2a64e3c94a6661db70e93d07f5e3608202fe8871
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
2021-11-08 21:31:43 -05:00
Sandeep Gangadharaiah
ce678e896e disp: msm: dp: check for active panels ptr before cleanup
During a probable race condition where usermode is triggering
a delayed cleanup, this instance would be empty leading to a null
pointer dereference. This change will add protection around this
pointer.

Change-Id: I8e90a1ba3ca925f08678e5fa67616420204edae7
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
2021-11-08 21:30:33 -05:00
qctecmdr
84973878ad Merge "disp: msm: dsi: Logging Improvement in dsi driver" 2021-11-08 13:26:05 -08:00
Prabhanjan Kandula
6acf9fddfd disp: msm: update rsc vsync timeout value dynamic
Considering requirement for supporting panel refresh rates upto
1Hz current default timeout value is not sufficient. Based on
panel refresh rate update vsync wait timeout value so that
any vsync waits from here on will have adjusted timeout value.

Change-Id: I65af152c4bd3decdd7135a4cc38f54e3bb3d5c92
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
2021-11-08 12:17:46 -08:00
Nilaan Gunabalachandran
0ba21c667d disp: msm: increase size of sde_kms_info
With requirements to support an increased number of display modes,
the current size of sde_kms_info is insufficient. This change
increases the sde_kms_info max size.

Change-Id: Ie0f29003732870dad9ce31ee7d484e84f12ba542
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2021-11-08 14:59:49 -05:00
Yashwanth
50aa3cd210 disp: msm: sde: fix traffic shaper prefill calculations
This change fixes traffic shaper prefill calculations
for prefill count and bytes per clock as per hardware
recommendations in the HPG which are calcualted as below:

ts_ count = ts_end*19200000/fps/(vtotal)

ts_bytes_per_clk = ceil(h_src*v_src*bpp*fps/
			19200000*amortized_pref_rate)

Change-Id: Icc2348421a2124daa3b0056f46d7a6a45021381b
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-11-08 17:29:22 +05:30
qctecmdr
cb24fd2bc6 Merge "disp: msm: sde: add rev checks for cape target" 2021-11-07 04:30:56 -08:00
qctecmdr
4abbe9ee47 Merge "disp: rsc: update mode-1 threshold config to 1 hz" 2021-11-06 06:25:54 -07:00
Steve Cohen
f47009b55f disp: msm: sde: fix constness of list_sort compare function
Kernel upgrade has updated list_sort's compare callback's
function signature to take const lists, preventing modification
when performing a comparison.

Change-Id: I71dbe33b9d213357ad9706ffc270053ea569006d
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
2021-11-05 20:08:18 -04:00
qctecmdr
45fd1bf563 Merge "disp: msm: sde: Add spr and demura to handoff features list" 2021-11-05 14:58:29 -07:00
Ritesh Kumar
986c7b1028 disp: msm: dsi: Logging Improvement in dsi driver
This change adds additional logs in dsi driver for
easy debugging of issues related to command transfer.

Change-Id: Ica784bed6c360b2760d6606d625837e23a22410c
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
2021-11-05 02:08:17 -07:00
Ritesh Kumar
13f4082d58 disp: msm: dsi: Fix post cmd tx sequence for read commands
For read commands, wait_for_done() should be called in dsi_message_rx function.
Currently, its being called twice from dsi_message_rx and dsi_ctrl_post_cmd_transfer.
This change adds a check to skip wait_for_done() from dsi_ctrl_post_cmd_transfer.

Change-Id: Icb7ccd0f8dde24c6c26732f7cb92a20bebb26f5d
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
2021-11-05 14:34:58 +05:30
Abhijit Kulkarni
683f6bc6af disp: msm: sde: send event on trusted vm transition
This change sends a notification to user mode after msm_drm
driver releases the mmio and irq resources on trusted vm transition
request. This is required as user mode has no other way to know
when the resources where actually released. User mode driver earlier
relied on retire fence signaling but retire fences are send before
releasing the hw.

Change-Id: Ia218cfcbf398b2de1ad9578fb9baedf348b067df
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2021-11-04 11:45:25 -07:00
Ritesh Kumar
f2499b50d8 disp: msm: dsi: remove early return from dma_cmd_wait_for_done
In ASYNC wait mode, next command kickoff can happen before previous command ISR execution is
completed in below sequence:

ASYNC command A -> triggered

dsi_ctrl_isr for command A -> fired and executed atomic_set(&dsi_ctrl->dma_irq_trig, 1);

wait_for_done for command A -> returns early as dsi_ctrl->dma_irq_trig is 1

ASYNC Command B -> triggered

wait_for_done for command B -> waiting for cmd_dma_done

dsi_ctrl_isr for command A -> executes complete_all(&dsi_ctrl->irq_info.cmd_dma_done);

wait_for_done for command B -> returns success incorrectly based on complete_all of previous
	command isr and disable_status_interrupt() is not called.

This leads to refcount of dma_done going wrong and dsi_ctrl_isr is not enabled on suspend resume.

To fix this issue, mark command transfer successful only based on complete_all(cmd_dma_done). This
way disable_status_interrupt() will be always called either from dsi_ctrl_isr or wait_for_done().

Change-Id: I0379ea7ff82a1e077b95f6996d11d1722de00936
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
2021-11-04 17:50:11 +05:30
Raviteja Tamatam
f5d5133807 disp: msm: sde: add rev checks for cape target
Add required revision checks from display for
cape target.

Change-Id: Ieb2b0b23462ff122b0090e7c78d8da41fa78fc07
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
2021-11-03 14:25:49 +05:30
Lakshmi Narayana Kalavala
a70e704ef0 disp: msm: sde: Add spr and demura to handoff features list
SPR and Demura modules being disabled when switching back from
Trusted VM to HLOS VM. The change adds the support to restore
the modules to restore to their original state.

Change-Id: I0a843671672179a4bc62da512baf02e911fb50aa
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
2021-11-02 17:15:56 -07:00