Change supports extending the enum for LTM2/3 and RC2/3.
Change-Id: I45df1808fa3a7e23f20afef084edaf091a59d7dd
Signed-off-by: Xu Yang <quic_yangxu@quicinc.com>
Expand reg dma data structures to support DMA 4,5.
Change-Id: I3aa7e879eb5ab7f89a7152e202759e885b05c75a
Signed-off-by: Renchao Liu <quic_rencliu@quicinc.com>
MDSS.9.0 adds support for mdp vsync based HW timestamps
on top the existing support for panel vsync based timestamps.
This allows us to enable vsync timestamp calculations for all the
use cases including a few corner cases (e.g. programmable fetch)
which we couldn't support with the existing HW.
This change adds the new HW register support and modifies the
timestamp read logic to use mdp vsync on supporting targets.
Change-Id: I2cb1b56ca9154174331c4fc1d8f82319b6989247
Signed-off-by: Michael Ru <mru@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
Dedicated registers are introduced for DSC 4HS merge block
programming from MDSS.9.0. This change adds support in the
driver to identify the change using a DSC feature flag
and separates out 4HS merge block programming to use appropriate
registers based on the DSC HW feature.
Change-Id: Ia64a1ed4bc5f5f301ab422144916cdce2a1dadac
Signed-off-by: Michael Ru <mru@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
From Kalama, the HW scheduler abstracts the low level
PP_DONE/WB_DONE interrupts and generates a common
CTL_DONE interrupt per hw ctl. This saves the software
the irq latency delays to process the frame complete
operations when multiple encoders are involved.
If supported, this change enables and waits for the
CTL_DONE interrupt instead of PP_DONE and WB_DONE.
This change adds support to wait for CTL_DONE irq in
only command mode panels as we don't drive two WB blocks
with single CTL.
Change-Id: I084d6bfb6a9fb0b48f912fe5787401c460ec5b56
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
Clean up stale mask bits which were deprecated from
the HW for the past few generations.
Change-Id: Id6bc20557d1047f7bffbb9641248dfbe0170daf0
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Changes include support to correct the version
check for DP PHY changes for 4nm target.
Change-Id: Ib891d43bd5db10edc4b49a70f7a3b8af073167cd
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Update ubwc version 4 check to only check for
the major version.
Change-Id: I4050f7d1a0858741e20f621d186e0ec2b9f7b10c
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Add encoder-id and wb-id in all the eventlogs, errors and debug
messages throughout writeback phys encoder to help in debugging.
Add traces to all the IRQs in writeback to track them efficiently.
Change-Id: I919e4d5054407ea5b01889dfd17c8cab6b40ee52
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add downscale blur block validations in atomic_check phase of writeback
encoder. Downscale blur along with partial update is not supported.
NV12 output in WB is not supported with downscale blur as CDM block
usage is mutually exclusive with dsnc_blur. If destination scaler is
enabled, the ds src or dst should match with dnsc_blur src based on
the ds tap point chosen.
Change-Id: I1d643dc26738c0e77d8e9181b4c834693153209c
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
When downscale blur feature is enabled, calculate the mixex and crtc
width and height using the dnsc_blur's src width & height. Update the
sde_crtc_get_mixer width/height functions to return the correct size
based on the features enabled.
Change-Id: I52dd88cc52e1ca5cb37e381e92e0e3032e7b090f
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add changes to configure the downscale blur hardware block based on
the conifgs set by user-mode. Program the ctl's writeback flush and
active bits when dnsc_blur is enabled. Bind the pingpong block that
feeds pixels to dnsc_blur hw block. Disable the active bits and unbind
the pp block binding during wb disable.
Change-Id: I1961ab437e344b13d0c186c1675a5bf79b84ea74
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add downscale blur connector properties to expose the hw block count,
downscaling filters used and the ratios supported. Add a custom dnsc_blur
property to allow usermode to send the required configuration to program
the hardware. Expose only for the virtual connector as the dnsc_blur is
only supported with writeback block.
Change-Id: I35dd263d9d5aafdb59bacbb3a0528ffd2bcaf6a3
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add sde catalog entries for the downscale blur supported filters
and the corresponding downscale ratios. The PCMN supports ratio
from 1 to 128 and gaussian filter supports specific ratios in the
range between 8 to 64.
Change-Id: Ifdf1a8fc7cfc5f5bd1297f10c7946c2bf9b63dcd
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Extend the topology_control connector property to support downscale
blur block. This gives user-mode the capability to reserve the downscale
blur block. Add sde rm changes to reserve the block based on this
connector property during sde_rm_reserve.
Change-Id: Ica2d7c57e6f528eb917acb6aae7e860352895a06
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add device tree parsing code for downscale blur block and sub blocks.
Add restrictions to allow downscale blur block to be used only by the
writeback. Set allowed interfaces for the block while parsing from
device-tree to restrict usage.
Change-Id: Ifa4c89ec52863d245a40bd4715a4e31f542b8117
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add sde ctl hw changes to support downscale blur. The ctl flush/active
bits for downscale blur are part of the writeback flush/active bits.
Add a new ops to update the dnsc_blur flush mask.
Change-Id: I29483ab399c5503ef4cfe5804d25cd26ad6265b2
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Downscale blur HW block support is added from MDSS 9.x. The block
can be used to downscale the layer mixer output before feeding it to
the writeback block. It can be used for both writeback & concurrent
writeback usecases. Add hw files and the respective blocks in sw to
program the downscale blur block.
Change-Id: Ic5787e1655eff5ef0960b7569e48d2f35d23bfc9
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Define the data structure and relevant flags for user mode program
to configure the downscale blur block.
Change-Id: Ic2916f5ac8626b93ab8b7adc7270f1e4bf1ec23a
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add display config support for compilation on parrot target.
Change-Id: I994b18687187f89b2794a886286280901ca44edb
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
This change adds support in mdp and dsi driver to support
multiple SIS.
Change-Id: I432068cea17e1784d7570a472fbadaa86695df07
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Commit bfb91aa ("Fix a null pointer access in msm_gem_shrinker_count()")
moves the point at which msm_gem_object is added to inactive list. Moving
this ensures that initialization will be complete before adding the
object to the list.
This change makes commit bfb91aa adaptive for both kernel-5.10 and
kernel-5.15.
Change-Id: I8efb66e239e2f8f56a3989370a58b96932a19f76
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Commit 45160ca ("disp: msm: use linux IRQ interfaces instead
of DRM helpers") update the msm layer to use linux IRQ interfaces
as DRM IRQ helpers are removed in 5.15 kernel.
This change uses macros to control the calling of correct irq interfaces
for kernel version 5.10 and version 5.15.
Change-Id: I367021df783c0aa02f729920b673e6f1f7397e65
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Commit bf0d220 ("disp: msm: dsi: add _NO_ to MIPI_DSI_* flags
disabling features") update names of DSI flags to follow upstream
convention. Purpose of the name change is to more clearly indicate
what is not supported when the flag is set.
This change puts macros around MIPI_DSI_* flags to adapt the name change
of flags for kernel version 5.10 and version 5.15..
Change-Id: I1c9a8da3819a6b641ca9b6d81191bc944913b49e
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Commit d1d1173 ("disp: msm: update msm_gem ops and remove unused
drm_driver callbacks") Update msm_gem and msm_drv to comply with
latest 5.15 kernel.Modify dma_buf_vmap() and dma-buf's vmap callback
to use truct dma_buf_map. Rename dma_resv_get_excl_rcu to _unlocked.
Remove deprecated GEM and PRIME callbacks.
This change adapts all the interface change for kernel version 5.10
and version 5.15..
Change-Id: Icb495dc4e5d20999f773ed5881eff233ff3a48bc
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Commit 283560c ("disp: msm: dp: use Extended Base Receiver Capability DPCD space")
pass additional parameters to supply maximum lane count and rate to MST topology
manager. In cases where sources have lower maximum lane count or rate than default
MAX_LINK_RATE, these values will be used instead.
This change puts macros in the callers of function drm_dp_mst_topology_mgr_init to
handle interface change between kernel version 5.10 and version 5.15.
Change-Id: I394c70640606de477d67b08cafb495bebb6c549f
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Commit ddac29b ("disp: msm: Pass the full state to crtc plane and connector
atomic functions") pass full state to crtc, plane, and connector atomic
functions and retrieve drm_crtc/plane/connector_state within the atomic
function.
This change puts macros in the callers of atomic functions to handle API
changes between kernel version 5.10 and version 5.15.
Change-Id: I8e710e33f0a149bbfaa54820a7174a05810e2da4
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Commit 1ef7ff2 ("disp: msm: dp: pass drm_dp_aux to drm_dp_link_train* APIs")
passes additional parameter drm_dp_aux to drm_dp_link_train APIs in order
to use drm_dbg_* within those functions.
This change put a macro in the drm_dp_link_train* APIs caller to handle API
changes for both kernel version 5.10 and version 5.15.
Change-Id: I9fd22e0effbe87b6cfecf72b38a10d74a2c0c5ea
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Changes include support for 4nm DP PHY and DP PLL.
Added dp_pll_4nm.c file with register programming
sequences for DP PHY and PLL.
Change-Id: I104cf69964904c9a47a17e75a84df011d7994c9f
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Add dsi ctrl version 2.7 and dsi phy version 5.2 support for
Kalama hardware.
Change-Id: Ia7b4c8a2e1579458f114e466de8b24855e9251ce
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Changes include support for specific DP PHY
registers and related code changes for 4nm
target.
Change-Id: I9b349e47ff057421fa465a59e1206fd09f7e367a
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Currently, in dsi_display_get_modes, priv_info, rates,
front_porches and pixel_clks_khz memory is allocated for each
timing node and the same memory is copied for each supported fps.
The values of front porches calculated to maintain constant fps for
each bit clk rate gets overwritten with the values for last fps in
the dfps list. But the values of front porches should be different
in case where DFPS and dynamic clock are both supported either by
vfp approach or hfp approach. To fix this, allocate memory
separately for each fps.
Change-Id: Ibf753aa8cca8d77b02b20785b5435f1aba05106e
Signed-off-by: Kashish Jain <kashjain@codeaurora.org>
Extend the existing sys_cache_enabled debugfs node functionality
to enable/disable all the display related system cache. Boolean
property is converted to integer and each BIT is associated with
a system cache.
Usage:
enable SYS_CACHE_DISP:
echo 1 > /d/dri/0/debug/core_perf/sys_cache_enabled
enable SYS_CACHE_DISP_WB:
echo 2 > /d/dri/0/debug/core_perf/sys_cache_enabled
enable both:
echo 3 > /d/dri/0/debug/core_perf/sys_cache_enabled
Change-Id: I41eaacc4d3f448bb566993b20aa74caa979f1258
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add a cache_flag in msm_fb object to store the system cache state hints.
Writeback connector will store cache write hints if system cache write
is enabled while HW is writing into this buffer. Plane in the primary
display path, in a 2-pass composition strategy will use this cache hints
to enable the display HW to use system cache for reading the pixel data
from this buffer.
Change-Id: Iff92a453a36d4a60b5a0162832eebd5e8739b5c3
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add a custom cache_enable property in writeback connector to allow
user-mode to control the cache setting on a frame basis. Configure
the hw and activate/deactivate the llcc based on the property. The
custom property is added based on the availability of the system
cache for writeback.
Change-Id: I812b31955eb36c75c33ac279b56502a13f7cdcbf
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
