Dump csiphy registers on following fatal errors:
1. lane overflow error
2. unbounded frame error
3. SOT ans EOT reception error
4. stream underflow error
These errors irqs are set at csid end, Currently there is no
interface to send message from one subdevice to other if the subdev is
not a real time device. This change adds an interface to notify the
no real time subdev.
CRs-Fixed: 2696744
Change-Id: I522167d1639ac298bc739a8a5a380a01356f0776
Signed-off-by: Vishal Verma <vishverm@codeaurora.org>
Signed-off-by: Jigar Agrawal <jigar@codeaurora.org>
Fixes exit call flow as a part of rmmod.
CRs-Fixed: 2675526
Change-Id: I47111a737cb06d9bb3d0a417a471c5c9fb545999
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
msm: camera: tfe: Fix variable initialization issues
msm: camera: isp: Dual tfe event check with proper hw idx
msm: camera: smmu: Add support for non-contiguous mermory region
msm: camera: smmu: Use iommu best match algo for camera
msm: camera: ope: Optimize allocation of IO configuration
msm: camera: ope: Fix for KW Issues
msm: camera: ope: Add support for stripe level height configuration
msm: camera: tfe: Enable the delay line clc
msm: camera: ope: Fix false alarm for OPE HW timeout
msm: camera: tfe: Support register dump per request
msm: camera: ope: Increase max number of stripes
msm: camera: ope: Change packer and unpacker format in case NV12
msm: camera: tfe: Add packet code get command for tfe
msm: camera: ope: Trigger recovery in case of violation on write bus
msm: camera: ope: Protect ope hw reset with mutex
msm: camera: ope: Add a check for valid request in cdm callback
msm: camera: ope: Remove the BW & clock vote in release context
msm: camera: ope: Reduce OPE BUS memory
msm: camera: ope: Fix return value for ope acquire
msm: camera: ope: Fix false alarm for OPE request timeout
msm: camera: ope: Avoid deadlock during recovery after HW hang
msm: camera: tfe: tfe debug enhancement
msm: camera: cdm: Fix irq_data value in case of inline irq
msm: camera: flash: Switch off flash on provider crash
msm: camera: ope: Initialize ope hw mutex structure
msm: camera: cdm: Flush all available FIFOs during reset
msm: camera: cpas: Add mandatory bw option for axi ports clocks
msm: camera: ope: Use vzalloc to allocate the write bus ctx structure
msm: camera: ope: Fix handling of init hw failure
msm: camera: tfe: Enable per frame register dump for rdi only context
msm: camera: cdm: Protect cdm core status bits with mutex
msm: camera: cdm: correct the error check in cmd submit irq
msm: camera: ope: Fix unclock access during HW reset
msm: camera: ope: Program frame level settings after idle event
msm: camera: ope: Delay releasing of resources for last context
msm: camera: isp: Increase default SOF freeze timeout
msm: camera: smmu: Add map and unmap monitor
msm: camera: isp: Add trace events across ISP
msm: camera: smmu: Profile time taken for map, unmap
msm: camera: ope: Start context timer on receiving new request
msm: camera: tfe: Reduce stack size during set axi bw
msm: camera: cdm: Check for HW state before dumping registers
msm: camera: ope: Reduce stack footprint during acquire
msm: camera: tfe: Disable clock if tfe2 is not supported
msm: camera: cdm: Avoid cdm pause incase of BL submit
msm: camera: tfe: Optimize CSID IRQ logging
msm: camera: ope: Move request id validity check outside of lock
msm: camera: tfe: Correct the tfe hw manager dump logic
msm: camera: ope: Synchronize flush and submit BLs
msm: camera: cdm: Protect cdm reset status
msm: camera: cdm: Handle cdm deinit sequence properly
msm: camera: tfe: Reduce reset timeout to 100ms
msm: camera: ope: Fix hang detection
msm: camera: ope: Make non-fatal logs as debug and info logs
msm: camera: tfe: set overflow pending bit to zero after HW reset
msm: camera: ope: Do not disable CDM during error handling
msm: camera: ope: Add support for OPE Replay
msm: camera: ope: Stop OPE in case of init failure
msm: camera: ope: Synchronize process cmd and flush request
msm: camera: cdm: Fix CDM IRQ handling
msm: camera: tfe: LDAR dump for TFE
msm: camera: ope: Fix the length check for debug buffer
msm: camera: cdm: Fix CDM reset logic
msm: camera: ope: Dump debug registers in case of HW hang
msm: camera: tfe: Support the RDI bus port for line based mode
msm: camera: cdm: Handle out of order reset done events
msm: camera: ope: Consider other contexts during timeout
msm: camera: ope: Put GenIRQ in last stripe BL
msm: camera: tfe: Process the rdi interrupts for rdi only resource
msm: camera: jpeg: Check the HW state before accessing register
msm: camera: csiphy: Update csiphy power-up sequence for lito v2
msm: camera: cdm: Secure freeing of request lists using locks
msm: camera: cpas: Add support for Scuba camnoc
msm: camera: csiphy: Clear secure phy flags on release
msm: camera: tfe: validate the tfe bw num paths
msm: camera: ope: Reorder the reset order in ope acquire
msm: camera: ope: Dump debug registers in case of reset failure
msm: camera: ope: Add logic to detect hang in CDM
msm: camera: isp: Increase max count of cfg to support more init packets
msm: camera: core: Fix cpas axi clk rate overflow.
CRs-Fixed: 2668666
Change-Id: I882ca4bd117bebc7d1c62bc82299d69d7b5c9388
Signed-off-by: Trishansh Bhardwaj <tbhardwa@codeaurora.org>
There is high chances, when camera server crash flash may not have
flash off request scheduled with CRM. In case of torch on, followed
by shutdown sequence, if flash off request is not scheduled, flash
remains turned on. This change adds flash off operation, in case
of shutdown.
CRs-Fixed: 2691916
Change-Id: I472f2b204b93d0cdc3d8a1f14fff29ab479e4588
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
Update the master status data type, as it expects the negative value
and do the operation accordingly. Also, correct the return code and
update the validation check.
CRs-Fixed: 2686717
Change-Id: I8ecae74de2995a08e532a7f0ef078d48d45a928e
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
Turn off the flash while flushing if the flushed request is
flash off and removed flush request ID validation in flush_all
scenario.
CRs-Fixed: 2667472
Change-Id: Iaf123f2f56117d7b7d1ef6d2291b0cde8c232d44
Signed-off-by: Anil Kumar Kanakanti <akanakan@codeaurora.org>
Changes extraneous CAM_INFO logs into CAM_DBG logs in order to help
de-clutter serial boot logs.
CRs-Fixed: 2669269
Change-Id: I7589bd64363aa122c46e1193c68bbf49d78a4a9a
Signed-off-by: Karthik Jayakumar <kjayakum@codeaurora.org>
Lane enable register reset is not required any delay to reflect the
change. This change removes the unnecesaary delay from lane_enable
register. Also, adding 1us of delay between back to back write in
SW reset register along with condition based refelction of delay.
CRs-Fixed: 2671221
Change-Id: I010570045a97fc1489a84d22ebd39df6f6f14f0a
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
Update 2phase and 3phase bring up sequence for different
data rate to reflect latest hpg change.
CRs-Fixed: 2671221
Change-Id: Idd7445a523486a5fb4ec5d43bcf8987c54c089b0
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
External configs should be checked by using IS_REACHABLE/IS_ENABLED
macro's to check if the config option is set for the build target.
CRs-Fixed: 2584631
Change-Id: I07a0d95391a83a2264f826e2935d67686d295317
Signed-off-by: Karthik Jayakumar <kjayakum@codeaurora.org>
Secure CP control register always assume that it contains 7 bit
mask for each PHY. But this register format is different based on
target. Update secure CP control bitmask generation logic for each
PHY index based on phy_version.
So we have below 3 combinations to handle at SW.
1.Old Titan Targets : 7 bits for each PHY.
2.PHY 1_2_1 : for 4 pHYS 7 bits and for
remaining 2 PHYs 8 bits are reserved.
3.Mimas (PHY 2_0_1): 8 bits for each PHY.
CRs-Fixed: 2624698
Change-Id: Iac4c3c718fc96a51592e07b45458fb045c52366d
Signed-off-by: Anil Kumar Kanakanti <akanakan@codeaurora.org>
New usecase for flash driver requires to be trigger at EOF.
This change adds the new operation code support in flash
driver along with EOF enable support in crm and across
other drivers. Also to improve the performance, this change
adds the logic to dynamically update the subscribe event to
CRM, so that CRM can enqueue EOF events when Flash or any other
device add the request for EOF.
CRs-Fixed: 2633194
Change-Id: I2f68ac7fc6a4699debd39b64319728cdf17bbcfa
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
EEPROM Read using QUP I2C returns the number of bytes
read from the EEPROM, While CCI/SPI returns zero value.
Return Error only when if the value is less than zero.
CRs-Fixed: 2617882
External Impact: No
Change-Id: I9a9674366c10de4efce779f75dd36b293838c47b
Signed-off-by: Shankar Ravi <rshankar@codeaurora.org>
Turn off the flash while flushing if the flushed request
turns off the flash.
CRs-Fixed: 2576732
Change-Id: I546fc6b6ee79f492af905d163515eb19eed78f41
Signed-off-by: Depeng Shao <depengs@codeaurora.org>
Missing video unregister was causing list delete corruption.
Also, there were double free errors in Sync and CRM driver. Fix
v4l2 issues by adding the missing unregister calls and changing
release callback to empty, because we are freeing it during
cleanup. Improve logging during bind/unbind to better reflect what
is happening.
CRs-Fixed: 2584631
Change-Id: Idc5db655d22df54e8bdb470d29896e10f6987796
Signed-off-by: Mukund Madhusudan Atre <matre@codeaurora.org>
Updates maximum number of supported camera id to 9
CRs-Fixed: 2584631
Change-Id: I00a595d784b38030a7996a8da930ecdeaf05835c
Signed-off-by: Karthik Jayakumar <kjayakum@codeaurora.org>
Add support for qti flash along with updated max current DT
property. Remove support for enable/disable regulator as it
is no-op since a long time.
CRs-Fixed: 2584631
Change-Id: I3305e7b6e4d6ef34d90d38f5f25cfa5b8b817f8b
Signed-off-by: Mukund Madhusudan Atre <matre@codeaurora.org>
The devm_kfree call in remove is unbalanced without a devm_kzalloc.
Add required kzalloc and free during probe to balance it.
CRs-Fixed: 2584631
Change-Id: I14164405e62036f7918b858d978afe454e4feb4a
Signed-off-by: Mukund Madhusudan Atre <matre@codeaurora.org>
Toggle reset register in common and reset programming sequence.
CRs-Fixed: 2615460
Change-Id: Iba17fa3b2014be0bc27236169cf8456a7f8ededd
Signed-off-by: Tony Lijo Jose <tjose@codeaurora.org>
Due to the asynchronous nature of platform probes, inter
dependency between drivers needs to be taken care during
kernel boot up. Component helper provides the facility of
adding matching drivers in a list ordered in the way we want
to bind those drivers. The CRM driver acts as component master
to make sure all slave drivers are bound before it returns
from its own bind call. Add support for serializing platform
probes through component framework.
CRs-Fixed: 2584631
Change-Id: I345da1d2b9cccf6021ac6fc899143013b7714ec4
Signed-off-by: Mukund Madhusudan Atre <matre@codeaurora.org>
There is no need to wait till timeout in case of NACK or
underflow error irq is raised, so notify thread for rd_done
completion. Also, correct the error mask to catch the NACK
error for Master 1.
CRs-Fixed: 2598605
Change-Id: Ib8a16ee119dd81f1384283ac7e9f82d3ac2588bb
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
Signed-off-by: Depeng Shao <depengs@codeaurora.org>
As per HPG revision L, there's a difference in the DPHY combo-mode
sequence settings between lito v1 and v2. This change adds a
separate sequence for lito v2, csiphy version 1.2.2.2.
CRs-Fixed: 2591712
Change-Id: Ic535bd2c98f47c33aa689d0e1bfe07d7dac8d9a2
Signed-off-by: Shravan Nevatia <snevatia@codeaurora.org>
If any subdev is reporting Nack, cci hardware gets into resetting.
During resetting if sensor tries to apply Init setting, it fails.
This change adds retry for INIT setting to reapply after sometime.
CRs-Fixed: 2598605
Change-Id: Iff13014d74abe6aebaec6cd428811de9d865f090
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
Add a high-to-low transition in the CTRL0 register
during the common power-up sequence.
CRs-Fixed: 2580437
Change-Id: I66541d3d787fa2f161e5d8e647fb11c8075a1947
Signed-off-by: Shravan Nevatia <snevatia@codeaurora.org>
Correct the queue size for cci version 1.2 as below,
1. Queue 0 size = 64.
2. Queue 1 size = 16.
CRs-Fixed: 2594541
Change-Id: Ifc9407427fe2bf0996c77dc00c5dfe7e5ba22140
Signed-off-by: Tony Lijo Jose <tjose@codeaurora.org>
Currently image sensor need single source of the regulator per
category. Some sensor needs extra analog voltage for the functionality,
which require to draw power from multiple voltage regulator sources.
This change extends supports to add multiple voltage sources for
analog voltage.
CRs-Fixed: 2584631
Change-Id: I2d76cfb0fb971758c0d596ffd543aa3926a8886d
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
