In CPHY, packet header and checksum is sent twice and SYNC is
sent in between two headers. So, increase packet overhead used
in clock calculation to 15 bytes. Packet Header: 8 bytes,
CRC: 4 bytes, SYNC: 2 bytes and dcs command: 1 byte.
Change-Id: I7a1160cbb57ba4f1faeb4b36a16c322e6069d58f
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
The boot_disp_en flag for secondary display is getting enabled
all the time, even if its boot_param string is empty.
Correct the boot display name parsing from boot_param string
to fix this issue.
Change-Id: Ica1465611f592b22518061987571919838914891
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
ctrl and phy refcounts get incremented even on deferring probe
for display panels which need backlight through wled.As a
result, while probing, it considers that the device is already
in use. This change decrements the ctrl and phy refcounts for
defer probe.
Change-Id: Ica1f5712dd28ed4c635946f2ac89d5f4f074a4c5
Signed-off-by: Lipsa Rout <lrout@codeaurora.org>
In trusted-vm, there are no power cfg entries in device-tree as
there is no support. Add stub function to avoid parsing errors
related to power cfg in trusted-vm.
Change-Id: Id28ad9a4d5608d561e22b318a08c6bc1ccc5f2ee
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add VM ownership checks before accessing the HW through the debugfs
path in dsi display/ctrl modules to avoid illegal access.
Change-Id: Ia6e2ab0ef60d0f11e5945a63885d939db2ef78b0
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
The order of the panel timing nodes specified in the device tree is
not guaranteed to be the same while being parsed in the driver. This
results in unintended modes being set as preferred timing mode. The change
introduces cell-index property, so that the timing modes can be
accurately indexed and parsed.
Change-Id: I8ccd4d5a15643bfe72bc8be084f5e91fac26feb4
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Change adds support for transferring commands to each sublink.
Change-Id: Iefc0dca7343325cdfe0cf48d41d50e6e2a13bc05
Signed-off-by: Vara Reddy <varar@codeaurora.org>
Change adds support for enabling splitlink sublinks video data swap.
Change-Id: I731b85a5e8fe8638005433819957dd0658f72963
Signed-off-by: Vara Reddy <varar@codeaurora.org>
Panel GPIO's pins can be provided through DT or firmware data.
Use dsi parser util in consistent with other node parsings to
read their values.
Change-Id: I6dc687516aa0ce51fc56e54f4b5cbadc17f0dc1d
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
DSI display configuration can be either DT or firmware file driven.
When probed with firmware path, asynchronous firmware file read
callback function will be too late to check for dependencies and
defer the probe when the dependencies are not met.
Move all the dependency checks before the firmware file read request.
Since the panel data will not be available before the DT/firmware read,
this change limits the check to the dsi display layer.
Change-Id: Ib26ed7839389027c2fe2dc15f70a572df3990ed9
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Currently, RFI feature only supports panel that contains
a single timing node. This limits the feature availability
for panel with multiple modes or with DFPS support.
This change adds support for RFI on panels that contains
multiple timing nodes.
Change-Id: I3a7aadf7b6da3518350b2eb815602b13b5c259f5
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Add a new connector range property and a new entry to the panel
capability blob to publish the list of supported RFI frequencies.
In addition, add the required functions to set, validate and update
DSI bit clock rate value to trigger an internal seamless mode switch
and reconfigure DSI clock and PLL.
Change-Id: I7d19cc369f8c5528709f2f20a51ef02180ebdea4
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
When doing const fps RFI, dynamic refresh clock was done
in the next frame kick off, so as the orginal RFI work flow,
the clock setting also should be done here.
Change-Id: Ic3e6a35dc7264df028f5d848ac6f1eea04a95126
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Fix dlkm compilation errors that are due to the use of -Werror
flags used by the build system.
Change-Id: I5e1e9bc63c1361d73e4930aab123212717872ecb
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
This reverts commit 23734fc295.
Reverting this change as it does not address all the below uses cases for Waipio
- Supporting PROBE deferral based on dsi ctrl availability
- Dual DSI path with optional single DSI node
- Firmware DT blob parsing for single / dual dsi panels
Change-Id: Ifc747befadd85eb76995b6cb1f72407fa5dccdbb
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Currently, SDE_DBG_DUMP takes any number of hw block names along with
few defined strings as arguments. This set of arguments is used to
determine which HW block registers needs to be dumped. Move to a
blk bitmask to avoid passing a large set of arguments. The bitmask is
split based on the clks required to access the HW block for ease of use.
The lower 0-23 bits are used for HW blocks which can be accessed by just
enabling the MDP clks. DP is kept separate as it needs DP specific
clks to be enabled. Add a debugfs node through which the mask can be
modified, which can be useful while using the debugfs dump option to
force a panic.
As part of the change, remove in-log/in-mem enable mask debugfs node
for every debugbus and use a single node to control the logging
mechanism for all the HW blocks debugbus.
Change-Id: Ibb6354b3e3265c9911104bb0f964616eb8a898c9
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Clients of dsi driver can register to be notified of panel id
information. Dsi is probed early during the device boot-up. If the panel
id is available with dsi driver none of the clients have registered
that early. Once clients probe and they register with the dsi driver
panel id is not passed onto clients until power on of the dsi. Change
adds support to notify the dsi clients during registration if panel id
is valid.
Change-Id: Ic475060cbec5f5b645aed865939fffe66aef071b
For Demura continuous splash hand-off, the DTB must already have
a definition for a demura panel ID. This is necessary
as ABL currently only updates this node and will not add it in
if missing.
Introduce special handling to identify a panel ID of 0 as a dummy
node, and set all invalid cases to the panel id ~0x0.
Change-Id: I70315c1b32cce9bcd2f6142515f2355a489d470b
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
Previous design had the demura panel ID passed in on the Linux kernel
command line. Update the DSI driver to read this information from the
DTSI instead.
Change-Id: I7697bb34a313f1837b80ba5ff78e720e8131a819
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
This change populates qsync fps value in connector blob
to pass onto the userspace if qsync is enabled on the
target.
Change-Id: I2a14e7dbdbd7000562307c37e93f22182e3154b8
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
When DFPS and dynamic clock switch with constant fps are
enabled, wait for dynamic refresh done only if clock switch
is triggered. In case where only fps changes, clock remains
same. So, wait for dynamic refresh done is not required.
Change-Id: I1a96d8d6756086afe2cd6e5bdc19be27c2ffed92
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
PLL codes from devicetree are only required if dynamic clock is enabled
for video mode panels. This change ensures that unnecessary error logs are
not seen for all other panels, by parsing the data only if the panel property
is set.
Change-Id: I206520aab65b7a5613909c8ff527e88303533617
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change avoids hardcoding the PLL_LOCKDET_RATE_1 register
value, rather using the variable with the same name that has
been initialized in dsi_pll_regs.
Change-Id: Ideb2c2b593156a4361feeb071df41f65e52c3beb
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
While recalculating VCO rate, currently the frac_bits value
is being hardcoded. The change instead uses the initialized
value from the 5nm PLL configuration.
Change-Id: I245574f4810a7b036d512ff1a347aa7e296702d1
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
The DMA buffer allocation for DSI happens during the first
command transfer. This change moves this allocation to happen during
bind.
Change-Id: I7969a019a8b84282e8a153f5393c9a3de5a28043
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
The change updates DSI DPHY and CPHY programming for
PHY version 4_3.
Change-Id: Id6b5cfefdce9530891e1e0f5a34814606954d843
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
The maximum value of backlight scaling property is enlarged
from 65535 to U32_MAX. Change supports DRE feature to
increase backlight level through backlight scaling property.
Change-Id: Ibe929308faf8c6f94bacbec7f58cc4ffe8133a85
Signed-off-by: Xu Yang <yangxu@codeaurora.org>
Change rounds up the calculated byte clock rate to the nearest
even number.
Change-Id: Iea6d3121343f1b2cb6d0a06cd47a84b050d55ac1
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Change updates the pclk divider calculation to ensure
more accurate pclk rate for DSI.
Change-Id: Iaf3a5b6e4b10ac751b3a80e2c3041ab8260b21e5
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
For DPHY, DSI byte clock is used to derive the byte interface clock through
a DIV_2 divider. While setting the rate for byte interface clock, if the byte
clock rate is odd the recalculation of byte interface clock will fail. This
can further lead to recalculation of byte clock and result in unexpected
value for byte clock. The change ensures that for DPHY, the byte clock rate is
always even to avoid such issues.
Change-Id: I0a0371af75e5819ed1283b52b4681e70f55d66e0
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
