Remove the PRE_SSR blocking notifier call.
This is not required as early down event is not handled.
Change-Id: Ie448fa2af92edd484d282200cf350c6bddc5f99d
Signed-off-by: Vangala, Amarnath <quic_avangala@quicinc.com>
Remove handling for PRE_SSR event.
Move the gpio handling during SSR to SSR UP event.
Change-Id: I2bb1b66db455c6211f1bf12c9e19d7e306a6243a
Signed-off-by: Vangala, Amarnath <quic_avangala@quicinc.com>
add check to return from the hs_rem_irq( ) if the headset
removal is already reported.
Change-Id: If9ffc1a471b80f8c9d01875b531748327032926a
Signed-off-by: Ganapathiraju Sarath Varma <quic_ganavarm@quicinc.com>
Issue: when we change the UVLO_DEGLITCH_SETTING (0x3460) 6.8ms
and above, we can’t hear any audio playback from the Music app
even at max voltage (4.1V).
HW team suggest to change the UVLO_DEGLITCH_SETTING from 0x1B
to 0x1D and WSA884X_PA_FSM_TIMER0(0x3433) to 0xC0. By these
two settings playback is not getting mute.
Change-Id: I5d2d57c26d7f467ba3d2231f1642f34643f6d716
Signed-off-by: Ganapathiraju Sarath Varma <quic_ganavarm@quicinc.com>
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
Use correct Efuse register value for headphone
right-channel impedance calibration.
Change-Id: Ief075b18621dd55d5d636ab5e591b9bf07da5ac8
Signed-off-by: Eric Rosas <quic_erosas@quicinc.com>
When codec goes into suspend, disable vdd-px which
will cause an unvote in PM.
Change-Id: Ia9f958d67fc57dbf3932733797bce7b0eb742363
Signed-off-by: Eric Rosas <quic_erosas@quicinc.com>
Add impedance detection ramp down timeout after a given interval.
Change-Id: Ia03bc82ec0bb653e6ccd1b6d14c1a9cb996e8ecd
Signed-off-by: Sam Rainey <quic_rainey@quicinc.com>
Enable wcd939x surge reset routine. Add callback for
the event within mbhc and enable it for wcd939x.
Change-Id: Iabc8c3367ae2eca5982db4526c6860e5eba63b76
Signed-off-by: Eric Rosas <quic_erosas@quicinc.com>
For test program < 3, use local default trim values
for harmonium 2.0 version.
Change-Id: I8cdcbe83ddae4626cef1f3dc4bfab3b2c285a0ca
Signed-off-by: Phani Kumar Uppalapati <quic_phaniu@quicinc.com>
Update wcd939x register settings for 2.15V VDD_RX supply
and for 2Vpk and 1.4Vpk modes depending on the headphone
load impedance values.
Change-Id: Iae5e6087fe96d22c9b9f8b755c468d2e6dface4e
Signed-off-by: Phani Kumar Uppalapati <quic_phaniu@quicinc.com>
In lpass_cdc_wsa_macro_config_compander function,
add check for wsa_sys_gain array's index to make sure
it won't go out of bound.
Change-Id: I9d8512726de959e7a0d9e875e966140d70412e25
Signed-off-by: Deepali Jindal <quic_deepjind@quicinc.com>
Program WSA_DATA_FS_CTL reg based on input used(wsa rx/wsa2 rx)
and also update the channelmap based on mixer cntl.
Change-Id: I0cfac1d9b25dd1211824bcea2753bb6c1131f767
Signed-off-by: Ganapathiraju Sarath Varma <quic_ganavarm@quicinc.com>
Mix path clk is gated by main path clk, as per current logic we are not
enabling main path clk for mix path use-cases.
Enable main path clk before enabling mix path for UPD dedicated backend
to work.
Change-Id: I209d1eaf25f4ef08bbd534f5ecc858e465ce7e18
Signed-off-by: Faiz Nabi Kuchay <quic_fkuchay@quicinc.com>
Currently on pineapple CDP platform, sbu1/2 switches are always
pre-connected to gnd/mic of the jack. Avoid this static connection
and connect/disconnect only when headset insertion/removal is detected.
Change-Id: If3bef6834caeb539492304d8b16808cd09c5afab
Signed-off-by: Phani Kumar Uppalapati <quic_phaniu@quicinc.com>
Updated WCD937x, WSA881x-analog and bolero drivers for successful
compilation on kernel6.0 for holi.
Change-Id: Ia91a999f825570b3d7123842f0aad3740c4d25ed
In PDR cases INTR_CLEAR registers values are not updating
properly while doing reg_cache in recover from PDR. So add
these registers as volatile to get the exact HW values.
When these registe values are properly updated the FSM_PA
status is reseting properly and working.
Change-Id: I8fa7b01b3256ec8f01edc3fe48a519accfff9638
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
In SSR/PDR usb switch settings won't be reset in wcd939x-i2c
driver. So no need to do switch settings for AATC when recovering
from SSR/PDR. Depends on the status to avoid AATC switch settings
again after SSR/PDR.
Change-Id: If7fc2a84356a406e9cf7e6cc557e19584fda3969
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
Add static variable to store version to avoid improper
device pointer in wcd939x_readable_register().
Update WCD939X_NUM_REGISTERS macro to be correct size.
Change-Id: Ib594f2f799ac2202ff78c02ccf2f6cdb80ffd38e
Signed-off-by: Eric Rosas <quic_erosas@quicinc.com>
Few register default values are incorrectly set for harmonium
codec in the register map table. Fix it by setting correct
values as per the hardware interface documentation.
Change-Id: Ibcb517d6050a4932243ead396e6f89294aab4a23
Signed-off-by: Phani Kumar Uppalapati <quic_phaniu@quicinc.com>
During spk playback and VA concurrency,
sometimes WSA CLK goes out of sync causing
VI_TX data mute. To resolve this, everytime
after WSA MCLK enable toggle fs_cnt_clr bit.
Change-Id: Ia936f1d4843890d2ae5c02b039f502941a5427b9
Signed-off-by: Soumya Managoli <quic_c_smanag@quicinc.com>
