When destination scaler feature is enabled along with demura,
the crtc w/h will be lesser than the deumra layer w/h as it is
based on the panel w/h. Remove the invalid validation of
demura layers against crtc w/h to allow this usecase.
Change-Id: I5afd0407382a1bce458c97fcf8d571f5e7c0774f
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add bound check for number of dnsc_blur blocks, while parsing from
device tree. Fix out of bound access while setting the llcc_active
during system cache disable case in writeback.
Change-Id: I7e604db5ebfaa6e8b6f066e0f6efb76e7d78e604
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
When qsync is enabled with a large threshold start window, there
is a chance that two frames can be latched by mdp HW in single
vsync window. This change overrides the tearcheck rd_ptr_val
to a value larger than the end of the Tear check start window
to ensure new frame is not latched in current vsync window.
Change-Id: I21273f0bca83747210792b911e964dfd2d50079f
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
Add crtc checks to ensure the crtc width is always even number,
so there is no loss while dividing by num_mixers. Add checks in
dnsc_blur to ensure the src is always greater than the dest.
Change-Id: I876f19aa20857dc9ed2649c9cb7569348e7d5fd3
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add support for localized CLK_CTRL access through LUTDMA
hardware block.
This change aggregates RD/WR LUTDMA CLK_CTRL in a single
ops.
Change-Id: Id5c24bebf7dfcd9f768b2a6f6fa03f8b01747354
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Log the vblank timestamp during vblank callback. This will be
useful in calculating the precise difference between the vsync
while debugging. As part of the change, remove the vblank
counter logging in sde_crtc as it floods the logs with 4 entries
for each vblank request.
Change-Id: I6b532ad657581fb2a34318541acbd81a44858819
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
On composer kill event, drm lastclose occurs during which suspend
commit gets triggered on primary. If secondary display is stuck in
continuous splash, then we do a early return without triggering
this suspend commit. On composer start, userspace waits for power on
event, but the drm_driver has never entered suspend state, so power
on event is never sent to userspace. This causes HWC deadlock side
effect and the current change triggers null_commit on secondary
display and then issues a suspend commit on both the displays to
avoid this deadlock issue.
Change-Id: I126f43ba3dd2c3bfa83346e8fd4678f35527893d
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change adds support for triggering output
hw fence upon programmable line count.
Change-Id: Ie4b8252e4f9a448a8c11d17696b9bb0ded81b04b
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change updates the autorefresh disable sequence to manually
trigger output hw_fence during the transition. This is required
since on the last autorefresh frame HW will not trigger the output fence.
Change-Id: I6789fc6b51421524f88dcbdd1a063ae947646ae4
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change disables hw_fences when a mode switch
from video to command mode or command to video mode
is ongoing.
Change-Id: I6f99226b59b381c6d2ff34a85753f8608080f546
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change adds the value of hw-fence ready to
event logs for video and command modes.
Change-Id: I40a2e886a3b95e8853efcbdddf7fd9f6ce48eb9b
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change adds one-to-one memory mapping for the hwfence
ipcc register memory needed for hw fence feature.
Change-Id: I0e264183e02d0ed5f2254b409cc5e776d670f0dc
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Starting mdss 9.0, dpu supports triggering
the frame fetch through hw-fencing. This change
adds support for this hw-fence feature.
Change-Id: Icc7d0b69fc2a51103d14612f5ac89b44a47ed826
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change collects the OPR, MISR values. If the values are
different than the previous then notify to client with custom event.
Change-Id: I2546439be1f665d90e6505d65283d28096bf7cdd
Signed-off-by: Akshay Ashtunkar <quic_akshayaa@quicinc.com>
Toggle LLCC SCID for each consecutive LLCC write
operations and force read allocate when NSE bit
set.
Change-Id: Ice473cb126b627056b7346f142bc84c120e05f0b
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
This change adds reg dma support for vig DE lpf.
Change-Id: I9108046bb2afb987eec49224df4a45c37f9c27cd
Signed-off-by: Renchao Liu <quic_rencliu@quicinc.com>
This change updates vsync source as part of rc post modeset. For some
use cases like idlepc with DFPS, vsync could be configured for
previous fps and can cause timeouts during next frame.
Change-Id: I110fd958d2970eaca50ace0e72c4faea3fc64ce8
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
Avoid various possible nullptr dereferences.
Addresses various issues highlighted by static analysis.
Change-Id: I36d34d610b37bf2799a7e34cd1de8b909b5c0ae4
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Check the precise vsync feature bit in sde hw catalog features
bitmap for checking the precise vsync feature and remove the
obsolete has_precise_vsync_ts variable.
Change-Id: I1f0cfabe5dcf387358548e8ff5ea0d65d4d7cecf
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Currently only LLCC_DISP SCID is used to read and write to
system cache during static display use case.
This changes adds SCID LLCC_DISP_1 to allow each SCID to
have a dedicated function (read/write).
Change-Id: I5604ec1183d99a8492b005ec06ac94e5db60b5f7
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Currently a boolean variable is used to track if the system
cache feature is enable for a particular SCID.
This change converts it to use a feature bit instead.
Change-Id: I8461fd9fb837b871c4ac5c67a9ab7613aadea7bb
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Merge reg_dump and dbgbus dump flag into dump_mode, and bring
back debugfs node "evtlog_dump" to keep flexible controlling
of evtlog.
Set in_mem option as default dump mode, since in_coredump
option will be enabled once HW recovery feature is enabled.
Change-Id: I75de1a69b01594b652479bf79201591ac0bf62e5
Signed-off-by: Bruce Hoo <quic_bingchua@quicinc.com>
Currently, when doze mode is enabled the encoder off work
worker is started 1 ms after idle power collapse because of
aggressive idle-pc feature. This causes the system cache
worker to start after the clocks and vsync interrupt are disabled.
This change independently enables clocks and interrupts during
system cache work thread to decouple it from the encoder
off work sequence.
Change-Id: I8ed172b0e7c5c8e4e270e768434301d972e90eb9
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
UBWC revision is in the expanded form, no need to process it again.
Change-Id: Ie4aafeea5459a76f325a07e58af1de5665fe45ba
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Plane cache state is updated based on the crtc's cache state.
The plane is left with state cache state, if the particular plane
is not used in the subsequent frame by the same crtc. Reset the
plane cache state on plane disable and reset_custom_properties to
avoid this case.
Change-Id: Ic6d31567af23906e94c5404d1d366e030b9be199
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Static display usecase uses concurrent writeback path to compose the
layers and updates the primary display in the next cycle with cwb
output. Use LLCC_DISP scid for system cache in cwb path, to keep it
in sync with the legacy static display path. Use LLCC_DISP_WB for
the offline-wb path. Expose the writeback connector cache property
only when either or both the cache types are enabled.
Change-Id: I8ca4b14828a14ce0bde829136fb4baef272166aa
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add sde hw catalog change to enable LLCC_DISP_WB system cache, which
is used for 2-pass composition usecases with offline writeback path.
Change-Id: Ic320b95a6699e59c62fed41f7fb88c484d98ffd0
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Currently, when CWB system cache use case is enabled and multiple planes
are used to fetch the LLCC data only one SSPP is programmed correctly.
This change ensures that whenever the fb_cache_flag is non 0, the SSPP
system cache gets reprogrammed.
Change-Id: Ic90eaae207f6221efb1fc8749093d8b44e092e44
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Add line insertion support for sspp, this is used to support
display with external splitter. Line insertion logic checks
the difference between screen logical height and physical
height. If any difference is observed adds dummy and active
lines on screen.
Change-Id: Ieec322273df000a53fb39e05174c2d67c3c2da81
Signed-off-by: Rajesh kv <quic_kvrajesh@quicinc.com>
