Because of changes to ref clock frequency, few of the pll
reg values are different for kalama compared to palima.
This change differentiates between these two 4nm versions,
based on pll revision and also introduces a pll reg table
to differentiate the values.
Change-Id: I016330ded10ab334012daa8cc288a8cd5c039f58
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
DP PLL driver is the clock provider for link_clk and pixel_clk source
clocks. Once the PLL is configured, the clock rates for these output
clocks must be explicitly set using the clk_set_rate() API so that
the clock framework can correctly compute any MND values required
to satisfy the requested rate at the branch clocks that source from
the PLL output clocks.
Change-Id: I14f8f58333ac5ba3f547d12a123cb5e5f05c6005
Signed-off-by: Aravind Venkateswaran <quic_aravindh@quicinc.com>
Change removes the dependency of reading MVID and NVID settings
from dispcc registers and calculates the values locally in displayport
driver.
Change-Id: I9ad66aea44a3cbc0f739060c49e23d389022a48a
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
Certain pll variables and function signatures are
obsolete and hence removing the header file
declaration containing these.
Change-Id: I93d4ff096ff253f21d67660287d6d3baa857cca1
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
The divider value for vco clock is only dependent on the link rate
and is known during pll configure. Instead of depending on the
clock framework to program this divider as part of stream clock
enable, this change moves the configuration to pll configuration
and removes the set rate call on the vco clock.
Change-Id: If687a8ab057fdfd6c3b3ad2bd1c51663d9182ff4
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
With the change in the clock names for newer targets, this fix
updates the driver to support different clock names per target.
Change-Id: I58c35fce34356f8c79adb0ac8a907e2fb60813ae
Signed-off-by: Sudarsan Ramesh <sudarame@codeaurora.org>
The current pll driver models the entire DP clock
hierarchy using the clock framework. This creates
unnecessary dependency between the dp driver and
the clock driver and also limits the flexibility
to dp driver when configuring the DP clocks.
This change models these clocks as single nodes
and provide full control to the dp driver and
also minimizes the dependency on the clock driver.
Change-Id: Id5221441ea33b576e7c543396a12cbeb7b44d319
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
Add support for PLL programming in the DisplayPort driver.
Change-Id: I4f08a621dcae5d1f54d67bb5c34409249012cc7b
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
