Panels supporting Cphy use a specific divider
blocks. Add additional divider blocks for byte
and pixel clock output to support DSI CPHY.
Change-Id: I74b3ee2bdd22ae8fa20567fe837e03915537c4fb
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
The clock framework nulls the clock hardware init data, after a variant
of clk_register is called on the clk_hw pointer. This results in a null
pointer dereference when we try to call set rate in the PLL prepare
function. The call can be a direct call to the function rather than
trying to access through the init_data pointer of the clk_hw.
Change-Id: I3613eea915d4f5620d7f0258ae391ad2ac624148
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
DSI PLL is tightly coupled with DSI PHY. This change removes
separate DSI pll driver and makes DSI pll as a subnode to DSI
PHY which is an accurate way of representation. In addition, this
change adds support for 5nm DSI ctrl and PHY revisions and adds
DSI pll support for 5nm. Remove support for older DSI pll revisions
such as 7nm, 10nm, 14nm, 20nm, 28nm.
Change-Id: Ic8b886a9fe24b906e4ec5130720600efa1e59b68
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
