Do not send prerequisite htt message informing
support of Umac reset feature to firmware
if DS is enabled
Change-Id: I1272579a3079e126b81a3b324009f6f32c65a904
CRs-Fixed: 3425584
The kernel-doc script identified a large number of kernel-doc issues
in the dp/wifi3.0 folder. A series of patches have addressed most of
the issues, so now fix the remaining issues. Just like in the previous
patches, there are a number of instances where public functions have
their implementation documented instead of having their interface
documented, so make sure that the interfaces are documented.
Change-Id: I4bc39b0e1a9d8c264b72ec6db76ff7e92d24f277
CRs-Fixed: 3373822
Make DP changes for handling umac reset in QCA5332.
Changes are done to program msi_data value of the IPC interrupt to FW.
Change-Id: Ib6453755e191da655b87b528a7cef38a464f316b
CRs-Fixed: 3401146
Call UMAC reset initialization API from soc_attach_target().
FW exposes a service bit for this feature, use that to conditionally
enable this feature. Also, add default log levels for this feature.
CRs-Fixed: 3253464
Change-Id: Ia7c9cf07a7ab7b000ebe452ab074a82173b70129
UMAC reset prerequisite setup command contains the following information.
- Interrupt number to be used for raising the UMAC reset interrupt
- Address of the shared memory
This is an HTT command. Send this command as part of the UMAC reset
initialization sequence.
Change-Id: I7a08f48b420580b5e3dbb9b46f6605d986f8fd89
CRs-Fixed: 3244930
UMAC HW reset is expected to send the following Tx commands to the target.
- PRE_RESET_DONE
- POST_RESET_START_DONE
- POST_RESET_COMPLETE_DONE
Add the necessary logic for the same.
Change-Id: I2450ed9281691abcc064661d4481ae78f48a0f3d
CRs-Fixed: 3244895
UMAC HW reset is expected to receive the following 3 events from FW.
- DO_PRE_RESET
- DO_POST_RESET_START
- DO_POST_RESET_COMPLETE
Add necessary logic to handle these events.
Change-Id: I786ecf6ed2925fd7fcc0934fdce65c76784f4f67
CRs-Fixed: 3244865
Create a HIF context for UMAC reset handler, register the datapath UMAC HW
reset callback handler with HIF layer, request for UMAC HW reset interrupt,
and schedule a high priority tasklet to process the interrupt in which
call the registered DP callback handler.
CRs-Fixed: 3184312
Change-Id: Iefc811bf0d1b093c3c63bf2238c94a1448f4f139
UMAC HW reset feature will be using the last interrupt context in each
DP interrupt combination i.e., on a system with more than 8 MSIs for DP,
UMAC HW reset will be assigned a dedicated interrupt context.
Add the necessary support for the same.
CRs-Fixed: 3163900
Change-Id: I26abd01e4261661ed95e1aa3cb2a774e78b50d9f
