3 次程式碼提交

作者	SHA1	備註	提交日期
Aditya Bavanari	cfc65e8257	asoc: codecs: Vote for codec core and NPL clocks before regcache_sync ... Vote for codec core and NPL clocks before regcache_sync to avoid unclocked access of bolero registers. Unvote once the regcache sync is done. Change-Id: Iae45f487113c55318f33cd1950e2d6b64bcd945a Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>	2019-10-11 20:11:10 +05:30
Meng Wang	8ef0cc2ed4	asoc: bolero: reset all clks after SSR/PDR ... After SSR/PDR, the lpass clocks will be in off state. Force restart clocks after SSR/PDR, if enabled before SSR/PDR, to reenable the clocks. Change-Id: I3d850d92bdc6324aa7a64a83a9066f388a85c7f7 Signed-off-by: Meng Wang <mengw@codeaurora.org>	2019-06-06 08:45:19 +08:00
Vidyakumar Athota	5d45f4c865	asoc: codecs: bolero: add clk resource manager driver ... Add Bolero clock resource manager driver to handle/manage bolero clocks for all the concurrency usecases like record + voice activation. Change-Id: I970a05d96fc9060b44bfe670d465f0b9d72cc53b Signed-off-by: Vidyakumar Athota <vathota@codeaurora.org>	2019-04-05 08:00:03 -07:00