Prefetch RX HW desc, SW desc and SKB in pipeline
fasion in the first loop of RX processing.
This has improved TPUT by 200Mbps and provided a
10% gain in CPU (single core)
PINE with other optimizations: 3960Mbps @ 100% core-3
PINE + pipeline prefetch: 4130Mbps @ 90% core-3
Change-Id: I47f351601b264eb3a2b50e4154229d55da738724
Adding a nbuf and nbuf->data prefetches in 2nd loop
of Lithium datapath RX improved UDP throughput by
about 250Mbps.
PINE default driver: 3189Mbps @ 100% core-3
PINE with prefetch: 3469Mbps @ 100% core-3
Note: PINE reo ring is mapped to core-3.
Change-Id: I7f166b52c3697facdce3954994755c9c1412c1f3
Take care of the MLO peer bit indication to be
concatenated with peer_id to access the peer map
object.
Change-Id: Ia603a728101e83829a8906d1b847f42389e78ca6
CRs-Fixed: 3039326
Implement core DP rx processing to functions in to corresponding
architecture specific be/li rx files. Keep common utility functions
in DP common files.
Change-Id: I40083e10772fd2b6ce2f1fa9e197f2ad92d0522a
CRs-Fixed: 2891021
