In WBM2SW Rx Error path for BE
specific functionality
1) HAL API's/Function pointers are replaced
with specific function calls.
2) Efficient read/write of WBM Error Info
from HAL Rx desc.
3) Minimize reading data from Nbuf TLV.
4) Peer_id fix for MLO clients with security
Change-Id: I760694073a06c1829f28e7e92cd1657560d8eb06
CRs-Fixed: 3472220
In WBM2SW Rx Error path for BE
specific functionality
1) HAL API's/Function pointers are replaced
with specific function calls.
2) Efficient read/write of WBM Error Info
from HAL Rx desc.
3) Minimize reading data from Nbuf TLV.
Change-Id: Ic8793ffcbeb2411c9b81fb32acae062e8a1f40cc
CRs-Fixed: 3362828
Currently dp_soc_init/deinit API's are called first for
common soc initialization/deinitialization and then architecture
level init/deinit APIs are called from base dp_soc_init/deinit.
But with RHINE architecture dp_soc_init/deinit API's are not common,
so we cannot call these APIs as base. To handle this scenario
routing all the soc level init/deinit from arch ops APIs and
arch ops APIs will take care of calling common soc_init/deinit.
Change-Id: Ibb10d452931630c917088b4d222c7fbd82621f6a
CRs-Fixed: 3404205
WCN6450 is a chip based on Rhine architecture. Unlike LI/BE targets,
chipsets based on Rhine (RH) do not have host facing UMAC HW blocks.
Their corresponding SRNG interfaces are also removed. The functionality
of these UMAC HW blocks is replaced with a software implementation in
the firmware. Communication between the driver and firmware will happen
over copy engine (CE).
Although there are no host facing UMAC HW blocks, the CE hardware used
in WCN6450 expects the host driver to use the TX descriptor (HW) format
of LI targets during TX packet enqueue. Therefore it is required to
create a new pool of TX descriptors (HW) pool for WCN6450 that is used
during TX.
The logic to create/free/init/deinit these descriptors is specific
to WCN6450/Rhine, therefore it is implemented in architecture specific
Rhine code.
Introduce new APIs in struct dp_arch_ops {} to allocate and free
arch specific TX descriptors. These ops will be no-op for LI/BE
architectures.
Also for Rhine targets, allocate/free other TX descriptors like TX EXT &
TSO descriptors as part of the arch APIs.
Change-Id: I452ac69143395881ab8580355a0f75571dc3e929
CRs-Fixed: 3381711
Add support of HW Link ID in PeerMetaData.
Retrieve the HW Link ID in both Rx per packet
path and RX Error path, store it in nbuf cb.
Use the stored value from nbuf while updating
MLO peer link statistics.
Change-Id: I11596d44fe8557af568fd399d0c0a04d2b887b2a
CRs-Fixed: 3397721
1) In WBM2SW Rx Error path, code to reap and
the process the HAL descriptor is split into
BE and LI architecture specific functionality
in dp_be_rx and dp_li_rx files respectively.
2) The function to handle Null Queue desc.
error for WBM and REO Rx Error path is split
into BE and LI architecture specific
functionality in dp_be_rx and dp_li_rx files
respectively.
Change-Id: Ic51a9742f65cee677ed7f3081f49fb3ece5b42f1
CRs-Fixed: 3356179
from Beryllium onwards a single Flow Search Table
will be used across multiple radios. to ensure this
a single FST attach is called for the first SOC's
pdev and FST detach is called only during last pdev
of last SOC. the same FST instance is saved in all
pdevs of all the SOCs
CRs-Fixed: 3366409
Change-Id: I42fbdc6f09fb902021877e100a2831a1a24bc975
Add support for GET MLO Multicast API to check
if the vdev is primary multicast vdev.
Enhanced SET MLO Multicast API to reset primary
multicast flag for all partner vdevs.
Change-Id: Ic88949ce922bb1d0fd34349058d254de0d1f563c
CRs-Fixed: 3322523
Ideally in MLO, Rx buffers should be routed to error
rings of the SOC which owns the RX buffer or link desc
incase of any error or fragment
But in case of HW issue if the packets are routed to
partner soc. Handle gracefully instead of assert
Change-Id: Ia56188808dfd034e960e1c1345de8f760e4b05f1
CRs-Fixed: 3327959
In 256M profile dp_li_rx.c file is not getting compiled.
Initialize dp_rx_chain_msdus_li() only when HOST mode is supported.
Change-Id: I96f71b9ea7869f0ba9fec05424b0a8c6f378f2f4
CRs-Fixed: 3314081
When compact rx tlv feature is enabled fetch the
reo qdesc from the peer instead of rx pkt tlvs.
Change-Id: Idc9eec559b71ebb2dc39ea1d648a384ea0eb9559
CRs-Fixed: 3311270
Adding compact tlv support for QCN9224, As part of this change
Rx tlv size will reduce from 384 bytes to 128 bytes.
Change-Id: I3f42a781e42b2e696a5b25d9c5f333c8cc83b7fe
CRs-Fixed: 3274152
Add support for:-
1. PPE VP entry attach and detach.
2. Per VAP PRI2TID Support
3. Dump the PPE VP HW entries.
4. Add tx completion handling for ppeds descriptors
Change-Id: I2a6d0be5bb556663a39a24d17b703877f3b5ad00
CRs-Fixed: 3276981
Compilation is failing when Monitor support is disabled
Moved monitor related API and structure to monitor header files.
CRs-Fixed: 3257872
Change-Id: Ie1b3dc16b38c88bfd73fc89aaa395d4b57a61e5c
Add framework to use different RX hash values and ring masks
for ML and non-ML peers
Change-Id: I098cb50b8873eb137ce096011d01a5c21aaf854f
CRs-Fixed: 3269916
This is a new FAST TX API which avoids various checks.
This API will be called when SFE tags a pkt as fast_forwarded
and vap's fast_tx flag is set.
avoid additional re-checks in the wifi TX function
CRs-Fixed: 3218650
Change-Id: Iba17ede59652a1ff2af553f57de21dc58946298e
- Add support to compute HW Tx completion delay on WKK
- Define arch op to calculate delay
Change-Id: I82567cc781e90fe01dc5a0edfffacd4cde73f652
CRs-Fixed: 3220911
In case Multi chip MLO configure same hash key for
all SOCs in MLO. This change is needed to avoid
same flow traffic distributed to multiple REOs.
Change-Id: Ib6cde4ae32e58ef2d45c02d640c133458f5bfac5
CRs-Fixed: 3201978
Ageout flush does not happen for WBM2SW4 if there
is only one TX completion pending in FIFO and all the
other WBM release rings are not active. This is due to
an issue in HW and this prevents suspend to happen due
to pending tx completions.
Fix is to avoid using WBM2SW4 release ring and instead
reuse WBM2SW0.
Change-Id: I250d8c9d460895449939212ebdb7abd62edb0234
CRs-Fixed: 3124733
Add support to update tsf timestamp on driver entry and
exit in data packet. This helps debug latency issue in
XR usecases
Change-Id: I9c966c1b8cb09dc5eab6104fdad36c19a1d68045
CRs-Fixed: 3090108
In WIN BE chipsets, replace the REO tid
queue programming in FW via WMI with writing to a
Host managed table shared by HW and SW. REO HW will
pick the tid queue address from the table indexed by
peer id and tid number.
Change-Id: I8107ca5116425538329b11ae3519f02b32573bac
Enable the 4th Tx. completion ring to save CPU load
Initialization and interrupt handling for 4th completion ring
is done here.
Change-Id: I2db27218a3c3e14d719d012f03454a6a7aa647fe
Prefetch TX HW desc, SW desc and SKB in pipeline fashion in Tx.
completion path.
This improves the UDP DL CPU idle% by ~4.5%
Change-Id: I48096e996cd835321ce2681d3981fa94c7189f54
In the case of RAW mode, VAP parameters encap type, dscp_to_tid map id
and cipher are not updating in bank register.
Added a API to update vdev param.
Change-Id: I702bee563e7451f403fa32292bf20680cd66e213
CRs-Fixed: 3078687
