Trigger callback to ISP each time when there is a change
in phy clock so that csid and tfe clock rate can be
updated accordingly. The argument passed in callback api is
the final phy clock rate that is applied.
CRs-Fixed: 2854066
Change-Id: Ia74465e4082e08b4c50338e0eb779f996afa2795
Signed-off-by: shiwgupt <quic_shiwgupt@quicinc.com>
Signed-off-by: shaduls <quic_shaduls@quicinc.com>
(cherry picked from commit 1fd5054f530a16a5bf90901ba4c8bf2025e136dc)
Dumping both ipe and bps clocks in case of frame process
failure. Added generic utility function to dump any hw's
clocks.
CRs-Fixed: 3297488
Change-Id: Ia952696b0288361bffaeadfd53041c72fd21f96d
Signed-off-by: Yash Upadhyay <quic_yupadhya@quicinc.com>
Signed-off-by: Alok Chauhan <quic_alokc@quicinc.com>
On current scheme, we put validation inside IO function, it's hard
to block subsequent accessing when facing invalid address and may
increase the number of cycles to do the register accessing as well.
This change limits the validation to only for the reg dump, we can
take following up operations when accessing wrong address for read
rather than printing uncertain logs.
CRs-Fixed: 3589725
Change-Id: I7d38a3ddb6c3f8e2915070f3c24629754abf76d7
Signed-off-by: Stark Lin <quic_starlin@quicinc.com>
(cherry picked from commit 159f8889a51178a92186e66e24e39bfdb01e87ee)
Currently, CESTA hw clients vote directly in util layer using clk crm
api, this change will enable CESTA hw clients to vote using mmrm api when
appropriate. This change affects setting the clk rate as well as
registering and unregistering a hw client with mmrm interface.
CRs-Fixed: 3385745
Change-Id: I5a9ad0e515e153dbbb937cab3a951d05677c817b
Signed-off-by: Atiya Kailany <quic_akailany@quicinc.com>
(cherry picked from commit 61b72dfada00da024e0bfe7449a4c6d845b492d2)
Kernel panic might be caused by improper register offset which
is not memory aligned during write or read operation, this change
adds a validation for the offset to avoid accessing invalid address.
CRs-Fixed: 3542219
Change-Id: I8761c8d416890bd4571be8a64118036c0173d303
Signed-off-by: Stark Lin <quic_starlin@quicinc.com>
Currently, cesta hw client rates are being set through mmrm, camera
passes clk rate required and voting happens on mmrm side. This reverts that
funtionality and allows camera to use qcom_clk_crm api to vote directly
in util layer without passing to mmrm.
CRs-Fixed: 3385745
Change-Id: I0b9c6f6f3fc3c7d1513abd7ccf1d2d7180851c61
Signed-off-by: Atiya Kailany <quic_akailany@quicinc.com>
Currently, lowest clk voting level supported is LowSVS, this
change will add support to a lower voting level, LowSVS_D1.
CRs-Fixed: 3480799
Change-Id: Ibdfe9d1d05aa45439a537cebe828cceea83f39d4
Signed-off-by: Atiya Kailany <quic_akailany@quicinc.com>
This change will allow clients voting through mmrm to use the new mmrm
api and vote according to their drv_type. This change affects
registering, unregistering and setting the clk rate to sw and
hw clients.
CRs-Fixed: 3385745
Change-Id: I11f76a0de3ba0d8d969093725d4c528afef51373
Signed-off-by: Atiya Kailany <quic_akailany@quicinc.com>
The function cam_mem_mgr_release can unmap the buffers when in use.
This change prevents unmapping the buffers when in use.
CRs-Fixed: 3489559
Change-Id: I2e72e795d39ac15abfa56c19043c419a03686966
Signed-off-by: Shivakumar Malke <quic_smalke@quicinc.com>
Sometimes need to avoid access clock/regulator/icc api, this change
add support bypass clock/regulator/icc wrapper through enable
some debugfs parameters and devicetree.
CRs-Fixed: 3445248
Change-Id: I0546975bf063625b39b771c776813e7dbff84e06
Signed-off-by: zhuo <quic_zhuo@quicinc.com>
In CPAS v980, CAMNOC is split into RT and NRT. Camnoc RT and NRT each
has separate register base. Camnoc RT is used by TFE, IFE lite, RT CDM.
Camnoc NRT is used by OFE, IPE, ICP, JPEG, NRT CDM. There are also two
IRQ lines for CPAS: RT and NRT IRQs.
Add CPASTOP SBM IRQ for RT/NRT, static QOS NOC settings for RT/NRT,
Cesta, and others in the header file for v980. CPAS registers two IRQ
lines and handles the incoming (RT/NRT) IRQs based on the IRQ data for
each IRQ. CPAS SOC looks for IRQ identifier property in CPAS node DT
to classify the IRQ type.
Global Camnoc info variable and qchannel variable now contain separate
info for RT/NRT or combined info.
Add NRT reg base for camnoc NRT base. Add TFE UBWC Encode error.
CRs-Fixed: 3403163
Change-Id: I3044c6314fa65c4e486bfa1bff2e828ac5e285cd
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
Update SOC util to be able to parse multiple irq names from DT and,
request, enable, disable multiple irq lines per soc.
All IRQ lines per SOC will have the same handler but different data,
so ISR will have their own private data to differentiate source of irq
in the same handling function.
CRs-Fixed: 3395596
Change-Id: Id9ca1cd3ef105d732a82decd7c8078bd29668326
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
Some dead code was removed and a memory leak issue was resolved
This solves issues related to VA_UNUSED.GEN and MLK.MIGHT.
CRs-Fixed: 3394193
Change-Id: I387587a3e359df9ad44a15e3e3f58b3422c81ad9
Signed-off-by: Atiya Kailany <quic_akailany@quicinc.com>
On chipsets having cesta hw block support, for cesta supported clks
clk frequency can be changed during veritcal blanking based on
CSID DRV events. For this to happen, camera clients need to setup
high and low clock votes through hw clients. Use corresponding clk,
crm APIs to setup high, low clk frquencies and do channel switch
to apply newly set rates. Clients can also set clk frequency through
sw client which will set the floor. This feature helps in saving
power for usecases where vertical blanking is high such as
Fast Shutter usecase.
CRs-Fixed: 3294948
Change-Id: I1bcf650b439991a23b2a0f0f9a5162bdcd60dc64
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
Remove dead code from the camera driver.
CRs-Fixed: 3328154
Change-Id: I7dea63fed8f6c35825db079f89f8c34f6730f155
Signed-off-by: Chandan Kumar Jha <quic_cjha@quicinc.com>
Currently, we are checking the clock struct pointer for NULL
returned from clk_get functions. certain critical clocks might
have NULL returned for clk pointer, since they are enabled during
boot itself. Update return check condition for err only and ignore
NULL value and skip its usage.
CRs-Fixed: 3296865
Change-Id: I5c1852f2348ae8aeeb0508a2f4a052a8c4f1989e
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
This change adds a checking for regulator count,
since the regulator array has fixed length, so
add a protection to avoid meeting index ouf of
bounds issue.
CRs-Fixed: 3250328
Change-Id: I123ffa993ee7b1deb06e3789fa4add6ca5ce6b9f
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
Remove unnecessary memsets of the structure variables
whose fields are assigned prior to their usage or they
are dynamically allocated with calls that set the memory
to 0. This memset usage optimization is to improve
performance.
CRs-Fixed: 3228092
Change-Id: Iec68c6d072863627959ce603cff28afd26a1c408
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
For some chipsets, qchannel handshake needs icp clk to be
enabled. Add support to enable icp clk while qchannel
handshake by adding as optional clk in cpas node. Whether
to enable icp clk or not is controlled through workaround
list populated for each chipset.
Add mechanism to retry qchannel acceptance if the first
auto try has failed, by explicity writing 0x1 to qchannel
ctrl register. This will bring back qchannel to good state.
CRs-Fixed: 3131613
Change-Id: Ie39a9789b2eb1bf9c0f6adb26fe6d6e1823eff70
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
Create common root folder under debugfs root named camera at probe. Add
utility functions to create subdirectories under the common camera root.
CRs-Fixed: 3093049
Change-Id: Ia4cefb5d2263ecabf1b9d70deefa1ee624b04f07
Signed-off-by: Anand Ravi <quic_ananravi@quicinc.com>
Targets which use same SPF with CONFIG_MMRM enabled - but one
chipset need to use mmrm, other doesn't need. In such cases,
calling this mmrm API helps to differentiate the flow.
Returns false if mmrm is not supported and true if mmrm is
supported.
CRs-Fixed: 3066104
Change-Id: I11ad3c02e66575905a01e1eb0b6a8e053acfbe46
Signed-off-by: Vikram Sharma <vikramsa@codeaurora.org>
Send clock rate as 0 for src clocks to MMRM, when disabling
the clock. This will help MMRM in peak overshoot computation.
CRs-Fixed: 2841729
Change-Id: I048b530fb620f0e47e1596f31e2ca12ff43bb471
Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>
Currently pinctrl state update operation is integrated
with platform resource operation. This can create unwanted
transition of pinctrl which can stay in suspend state.
This change detach and separate out the pinctrl entries
with index passed from devicetree. Pinctrl select
state operation is detach from platform enable/disable
operation to operate from device directly only for better
control with respect to operation.
CRs-Fixed: 2907475, 2954556
Change-Id: I918568f96e8888df6882f165458f5c4ab32d6348
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
Enable using mmrm APIs for camera clk set rates.
CRs-Fixed: 2901925
Change-Id: Id80f2d46b62aef9ebcbb238a342925c74aac053a
Signed-off-by: Pavan Kumar Chilamkurthi <pchilamk@codeaurora.org>
Use mmrm interface to set clock rate on all
camera clks.
CRs-Fixed: 2901925
Change-Id: I2e4c31a11e0e068693ac15356e3b3dafcfa0b078
Signed-off-by: Pavan Kumar Chilamkurthi <pchilamk@codeaurora.org>
Source clocks that are shared with multiple devices need
to be consolidated before setting clock rate on them.
If not, a set call with lower freq from one device
overwrites the frequency that previously set by another
device, causing issues. Clk wrapper helps to consolidate
the frequency among multiple devices and set the max
frequency required by all of them. A shared clock notation
is defined in DT and go through clk wrapper based on that.
CRs-Fixed: 2901925
Change-Id: Ia5b2b5fd3c0619c994e27d96fad6e11d126de182
Signed-off-by: Pavan Kumar Chilamkurthi <pchilamk@codeaurora.org>
With the newly added register base types for reg dump, the
validation needs to be changed to account for the new max.
CRs-Fixed: 2841729
Change-Id: I6babe7a1e4d6def51b8e433be4431f04a0a417e8
Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>
Clients like cpas scale some clocks like slow_ahb, fast_ahb
through vote level based on other hw's src clk freq while
the actual src clock (camnoc) is calculated and set directly
through set_src_clk API. This will overwrite freq of camnoc_axi
with the same level as AHB when ahb clocks are set. Do not
set src clk rate while setting rate for other clocks using level.
CRs-Fixed: 2793673
Change-Id: I5538a5cebf4e47c407a2bf9778136500b1162b4a
Signed-off-by: Pavan Kumar Chilamkurthi <pchilamk@codeaurora.org>
Currently, if dsp clock source is not found in device tree, still
we are trying to enable/disable clock source. Check for availability
of that optional clock before toggling it.
CRs-Fixed: 2762106
Change-Id: I2a4467f5383343bdf1e6607712270f574c76e51e
Signed-off-by: Mukund Madhusudan Atre <matre@codeaurora.org>
Enhance cpas state dump to get more information about
bandwidth and clock status. This additional state dump
can be enabled using debugfs.
adb shell "echo 1 > /sys/kernel/debug/camera_cpas/full_state_dump"
Traverse through all bw tree nodes and print info in each node.
Print current clk frequencies of all clocks that cpas enables.
Read rpmh bcm status registers to understand mmnoc clk freq.
Add cpas monitor to save important info whenever clients
notify with an event. This monitor info is printed in cpas
state dump.
CRs-Fixed: 2754299
Change-Id: Ib9007091f7e34127f1ca92498e2537b2a06887cb
Signed-off-by: Pavan Kumar Chilamkurthi <pchilamk@codeaurora.org>
Guards debugfs features in camera driver to only be compiled when
CONFIG_DEBUG_FS is enabled.
CRs-Fixed: 2717236
Change-Id: I0de77741301d259cbec64e8a2e27830981b2b69d
Signed-off-by: Karthik Jayakumar <kjayakum@codeaurora.org>
Fixes exit call flow as a part of rmmod.
CRs-Fixed: 2675526
Change-Id: I47111a737cb06d9bb3d0a417a471c5c9fb545999
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
msm: camera: tfe: Fix variable initialization issues
msm: camera: isp: Dual tfe event check with proper hw idx
msm: camera: smmu: Add support for non-contiguous mermory region
msm: camera: smmu: Use iommu best match algo for camera
msm: camera: ope: Optimize allocation of IO configuration
msm: camera: ope: Fix for KW Issues
msm: camera: ope: Add support for stripe level height configuration
msm: camera: tfe: Enable the delay line clc
msm: camera: ope: Fix false alarm for OPE HW timeout
msm: camera: tfe: Support register dump per request
msm: camera: ope: Increase max number of stripes
msm: camera: ope: Change packer and unpacker format in case NV12
msm: camera: tfe: Add packet code get command for tfe
msm: camera: ope: Trigger recovery in case of violation on write bus
msm: camera: ope: Protect ope hw reset with mutex
msm: camera: ope: Add a check for valid request in cdm callback
msm: camera: ope: Remove the BW & clock vote in release context
msm: camera: ope: Reduce OPE BUS memory
msm: camera: ope: Fix return value for ope acquire
msm: camera: ope: Fix false alarm for OPE request timeout
msm: camera: ope: Avoid deadlock during recovery after HW hang
msm: camera: tfe: tfe debug enhancement
msm: camera: cdm: Fix irq_data value in case of inline irq
msm: camera: flash: Switch off flash on provider crash
msm: camera: ope: Initialize ope hw mutex structure
msm: camera: cdm: Flush all available FIFOs during reset
msm: camera: cpas: Add mandatory bw option for axi ports clocks
msm: camera: ope: Use vzalloc to allocate the write bus ctx structure
msm: camera: ope: Fix handling of init hw failure
msm: camera: tfe: Enable per frame register dump for rdi only context
msm: camera: cdm: Protect cdm core status bits with mutex
msm: camera: cdm: correct the error check in cmd submit irq
msm: camera: ope: Fix unclock access during HW reset
msm: camera: ope: Program frame level settings after idle event
msm: camera: ope: Delay releasing of resources for last context
msm: camera: isp: Increase default SOF freeze timeout
msm: camera: smmu: Add map and unmap monitor
msm: camera: isp: Add trace events across ISP
msm: camera: smmu: Profile time taken for map, unmap
msm: camera: ope: Start context timer on receiving new request
msm: camera: tfe: Reduce stack size during set axi bw
msm: camera: cdm: Check for HW state before dumping registers
msm: camera: ope: Reduce stack footprint during acquire
msm: camera: tfe: Disable clock if tfe2 is not supported
msm: camera: cdm: Avoid cdm pause incase of BL submit
msm: camera: tfe: Optimize CSID IRQ logging
msm: camera: ope: Move request id validity check outside of lock
msm: camera: tfe: Correct the tfe hw manager dump logic
msm: camera: ope: Synchronize flush and submit BLs
msm: camera: cdm: Protect cdm reset status
msm: camera: cdm: Handle cdm deinit sequence properly
msm: camera: tfe: Reduce reset timeout to 100ms
msm: camera: ope: Fix hang detection
msm: camera: ope: Make non-fatal logs as debug and info logs
msm: camera: tfe: set overflow pending bit to zero after HW reset
msm: camera: ope: Do not disable CDM during error handling
msm: camera: ope: Add support for OPE Replay
msm: camera: ope: Stop OPE in case of init failure
msm: camera: ope: Synchronize process cmd and flush request
msm: camera: cdm: Fix CDM IRQ handling
msm: camera: tfe: LDAR dump for TFE
msm: camera: ope: Fix the length check for debug buffer
msm: camera: cdm: Fix CDM reset logic
msm: camera: ope: Dump debug registers in case of HW hang
msm: camera: tfe: Support the RDI bus port for line based mode
msm: camera: cdm: Handle out of order reset done events
msm: camera: ope: Consider other contexts during timeout
msm: camera: ope: Put GenIRQ in last stripe BL
msm: camera: tfe: Process the rdi interrupts for rdi only resource
msm: camera: jpeg: Check the HW state before accessing register
msm: camera: csiphy: Update csiphy power-up sequence for lito v2
msm: camera: cdm: Secure freeing of request lists using locks
msm: camera: cpas: Add support for Scuba camnoc
msm: camera: csiphy: Clear secure phy flags on release
msm: camera: tfe: validate the tfe bw num paths
msm: camera: ope: Reorder the reset order in ope acquire
msm: camera: ope: Dump debug registers in case of reset failure
msm: camera: ope: Add logic to detect hang in CDM
msm: camera: isp: Increase max count of cfg to support more init packets
msm: camera: core: Fix cpas axi clk rate overflow.
CRs-Fixed: 2668666
Change-Id: I882ca4bd117bebc7d1c62bc82299d69d7b5c9388
Signed-off-by: Trishansh Bhardwaj <tbhardwa@codeaurora.org>
Changes extraneous CAM_INFO logs into CAM_DBG logs in order to help
de-clutter serial boot logs.
CRs-Fixed: 2669269
Change-Id: I7589bd64363aa122c46e1193c68bbf49d78a4a9a
Signed-off-by: Karthik Jayakumar <kjayakum@codeaurora.org>
When user space detects an error or does not receive
response for a request, Lets do a reset(LDAR) is triggered.
Before LDAR, user space sends flush command to the
kernel space.
In order to debug the cause for this situation and to dump
the information, user space sends a dump command to
kernel space before sending flush.
As a part of this command, it passes the culprit request id
and the buffer into which the information can be dumped.
Kernel space traverses across the drivers and find the culprit hw
and dumps the relevant information in the buffer.
This data is written to a file for offline processing.
This commit dumps the IFE, CSID registers, LUT tables and context
information, cmd buffers, timestamps information for
submit, apply, RUP, epoch and buffdones of the last 20
requests.
CRs-Fixed: 2612116
Change-Id: If83db59458c1e5ad778f3fa90cbc730122491c54
Signed-off-by: Gaurav Jindal <gjindal@codeaurora.org>
Different CDM hardware have different capability and registers.
With old register space, handling new features and operations
would have been a complex task. This change takes care of old
version of CDM and also changes the regspace to provide every
register's access to CDM.
This change further adds support for "arbitration" in case of
multi-context CDMs.
Exports reset functionality to clients, detection of CDM hang.
Flushing the CDM requests and dumping the FIFO content for all
contexts.
It also adds submitting "debug_gen_irq" as BL_done IRQ is only
an indication for availability of FIFO's. The AHB operations
are completed can only be known if the added "debug_gen_irqs"
gets executed and are received by the CDM.
CRs-Fixed: 2594541
Change-Id: I9846b1c5320ba652c5d3b7d83d616d2dabc843e1
Signed-off-by: Abhilash Kumar <krabhi@codeaurora.org>
Signed-off-by: Trishansh Bhardwaj <tbhardwa@codeaurora.org>
Removed unused functions that called clk_set_flag, which has been
deprecated in linux kernel 5.x.
CRs-Fixed: 2554484
Change-Id: I0062383b0b059e6b359229f4b33470713289abb4
Signed-off-by: Karthik Jayakumar <kjayakum@codeaurora.org>
The command buffer obtained from user has several offsets and
sizes that need to be validated before accessing data. Also,
out buffer offsets need to be checked before writing data.
Add validation checks for parameters in command buffer for
reg dump.
CRs-Fixed: 2501003
Change-Id: I65b37befcefbd7f739663b6142d5d0eedcab25b4
Signed-off-by: Mukund Madhusudan Atre <matre@codeaurora.org>
Certain register values are required by user space during flush
to apply settings accordingly. Also, support for dumping registers
at the time of error is needed for debugging. Add support for
dumping register values in a range of offsets to given cmd buffer.
Change-Id: I5912118809f7a7dd701a555639d1057ffe665ce1
Signed-off-by: Mukund Madhusudan Atre <matre@codeaurora.org>
This change updates the scalable clock based on
hw src clock. Also, removed cam_soc_util_get_vote_level()
as it is duplicating the functionality with
cam_soc_util_get_clk_level() api.
Change-Id: I001264d150849770ef664ecc206a66f8a4f54412
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
Bring over camera driver changes as of msm-4.19
commit 5a5551a7 (Merge "msm: camera: reqmgr: Fix CRM
shift one req issue").
Change-Id: Ic0c2b2d74d1b3470c1c51d98228e312fb13c501a
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
