Grafico dei commit

11 Commit

Autore SHA1 Messaggio Data
qctecmdr
fc92a6d9f6 Merge "disp: msm: dp: Implement dsc slice selection logic based on sink caps" 2019-06-27 09:50:51 -07:00
qctecmdr
3c4d5f3557 Merge "disp: msm: dp: Ensure peak pxl rate does not exceed maximum supported by sink" 2019-06-19 05:21:38 -07:00
qctecmdr
f49f2c2153 Merge "disp: msm: dp: fix the dsc line buf bit depth selection for dp dsc" 2019-06-19 03:51:13 -07:00
Fuad Hossain
33284a9f4c disp: msm: dp: Implement dsc slice selection logic based on sink caps
The dp sink explicitly states the numbers of
slices it can support. When calculating the
number of slices for dsc configuration, ensure
that the sink supports the calculated number of
slices.

If the sink does not support the calculated
number of slices, keep rechecking sink support
for the subsequent slice increment, until we
reach the highest number of slices possible
according to the dp spec. If no compatible
sink slice support is found, do not enable dsc.

CRs-Fixed: 2325207
Change-Id: I485adacd258963cdec9cc52aa041373883ecadc7
Signed-off-by: Fuad Hossain <fhossain@codeaurora.org>
2019-06-17 12:25:44 -04:00
Fuad Hossain
5cb73d66bc disp: msm: dp: fix dsc parameters for 10bpp compression
Add configuration data to handle 10bpp 3:1
compression ratio based on hardware recommended
settings.

CRs-Fixed: 2325207
Change-Id: I7086dc235e0063a79c661fa8cee77d4e47e9c826
Signed-off-by: Fuad Hossain <fhossain@codeaurora.org>
2019-06-13 15:51:19 -04:00
Fuad Hossain
a9028ef4cf disp: msm: dp: Ensure peak pxl rate does not exceed maximum supported by sink
Ensure that the dp dsc peak pxl rate does not
exceed the maximum supported by the sink device.
If the mode's peak pxl rate per slice exceeds the
max, mark the mode as invalid.

CRs-Fixed: 2325207
Change-Id: Ic8904c759b8621c3aff258206599e1994f70e26e
Signed-off-by: Fuad Hossain <fhossain@codeaurora.org>
2019-06-13 15:19:26 -04:00
Fuad Hossain
b706052927 disp: msm: dp: fix the dsc line buf bit depth selection for dp dsc
The line buffer bit depth is used as part of dp
dsc calculations. Read the max supported line buf
bit depth supported by sink, and use that
restriction as part of the dsc calculations.

CRs-Fixed: 2325207
Change-Id: I4c995acad5f484edd1b438bdbf6c145b2d35ee41
Signed-off-by: Fuad Hossain <fhossain@codeaurora.org>
2019-06-13 13:37:44 -04:00
qctecmdr
9c05197ef9 Merge "disp: msm: sde: use wr_ptr interrupt instead of ctl_start" 2019-05-24 09:38:19 -07:00
Samantha Tran
3be27eafcc disp: msm: snapshot of msm and sde driver
This snapshot ports changes from 4.14 to 4.19 into
the msm and sde layer. Snapshot was taken as of
commit 0f8fb25421ff ("cnss2: Add device version to
SOC info structure").

Change-Id: I59b799a78319c2db6930a2a10bc38976f8c09898
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2019-05-22 13:08:31 -07:00
Ajay Singh Parmar
76837da1a9 disp: msm: dp: use extended DPCD fields to configure dp link rate
Use the EXTENDED_RECEIVER_CAPABILITY DPCD register fields,
if present, for enabling HBR3 link rate on supported targets.

CRs-Fixed: 2438457
Change-Id: I505d998f31f79162dc290fc47fd9fbba51527982
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
2019-05-08 22:05:27 -07:00
Narendra Muppalla
3709853456 Display drivers kernel project initial snapshot
This change brings msm display driver including sde,
dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel
project. It is first source code snapshot from base kernel project.

Change-Id: Iec864c064ce5ea04e170f24414c728684002f284
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2019-04-14 22:20:59 -07:00