Commit History

Author SHA1 Message Date
  Yujun Zhang 80d06ebb7c disp: pll: limit clock rate of shadow VCO clock 6 years ago
  Satya Rama Aditya Pinapala 7ea04a4d47 disp: pll: update DSI PHY PLL programming for Kona 6 years ago
  Aravind Venkateswaran a545123901 disp: pll: remove unsupported dividers for DSI pixel clock 6 years ago
  Yujun Zhang 6ec69969e2 disp: pll: add support for 7nm DSI PLL shadow clock 6 years ago
  qctecmdr ab3c7fdd80 Merge "disp: pll: update SSC offset value" 6 years ago
  Satya Rama Aditya Pinapala 2f3a90b47d disp: pll: update SSC offset value 6 years ago
  Aravind Venkateswaran 664040053b disp: pll: fix divider clock flags for DSI PLL clocks 6 years ago
  Aravind Venkateswaran acfd32f1b5 disp: pll: fix flags for DSI and DP PLL clocks 6 years ago
  Satya Rama Aditya Pinapala bda5e6a968 disp: pll: remove recalculation of vco rate 6 years ago
  Narendra Muppalla 3709853456 Display drivers kernel project initial snapshot 6 years ago