 Michael Ru
|
f470ecf038
disp: msm: dsi: consolidate DSI HW register macros
|
%!s(int64=4) %!d(string=hai) anos |
 Santosh Kumar Aenugu
|
6add9d0fc0
disp: msm: dsi: fix dsi pll dividers
|
%!s(int64=4) %!d(string=hai) anos |
 Satya Rama Aditya Pinapala
|
7471069739
disp: msm: dsi: fix DSI PLL configuring sequence
|
%!s(int64=4) %!d(string=hai) anos |
|
Satya Rama Aditya Pinapala
|
18d245cad8
disp: msm: dsi: parse PLL dfps data only if dynamic clock is enabled
|
%!s(int64=4) %!d(string=hai) anos |
 Yu Wu
|
f409da06b7
disp: msm: dsi: parse dsi pll codes from DT node
|
%!s(int64=4) %!d(string=hai) anos |
|
Satya Rama Aditya Pinapala
|
0a93edbae6
disp: msm: dsi: rework DSI PLL to be configured within PHY
|
%!s(int64=5) %!d(string=hai) anos |
 Rajeev Nandan
|
7cf728f3a6
disp: msm: dsi: add DSI PLL support for 10nm-LPU
|
%!s(int64=5) %!d(string=hai) anos |
|
Satya Rama Aditya Pinapala
|
5694bc2eee
disp: msm: dsi: move dsi pll as subnode to dsi PHY
|
%!s(int64=5) %!d(string=hai) anos |
