During dp_tx_hw_enqueue writing into HW SRNG,
if devcie is already runtime suspended, set the
SRNG_FLUSH_EVENT, so that it will be flushed
as part of dp runtime resume callback.
Change-Id: I95e74844cf74eb4f73862da3da9d93422f1eea8c
CRs-Fixed: 2664660
For 4 core CPU system, Tx access can be made lockless by associating
one Tx ring per CPU. Three Tx DATA rings and one SW2TX command ring
can be used for sending data to Tx.
Change-Id: I6e38cad52dffa4e46ff2b736cd6b949d061fa2a4
In pdev deinit path tx_desc->vdev can be NULL
in dp_tx_comp_free_buf use soc->osdev to unmap instead
of vdev
Change-Id: I8b390656d482fed3c8c85d928860222a88325ca1
During the packet transfer from HOST to Transmit Classifier Layer,
if NAWDS is enabled, send peer id of NAWDS peer.
This is to avoid re-injection from FW to Host.
Change-Id: Ic0e5c46fff3bbe1a3e8ea3a01986478c925452f5
CRs-Fixed: 2628703
Enable SW2TCL_CMD ring for data on QCN9000, QCA8074 V2/V1
and IPQ6018 targets.
Enabled 4th Tx ring for data enqueue to HW.
Transmit completions for packets from CPU0 and CPU3 are routed to
WBM2SW Completion ring 2.
WB2SW completion ring2 is mapped to CPU3.
Change-Id: Ied4c4704e1f8623e909ad45c547a611de26c7ec5
This is to enhance statics for runtime put/get, which is
to detect if there is mismatch for usage_count.
Change-Id: I24cddb9d10e4cb675c8375cbd0f589c7718bd680
CRs-Fixed: 2647972
Avoid memzeo of seg_info and msdu_info removing from default standard path
qdf_ktime_to_msg(qdf_ktime_get()); -- moved under a flag
Eth_hdr access made inside the Mcast enhancement check.
Change-Id: I12b6cc397d7eb626abdcdae001e92ef0d980e8a6
Restrict lock hold time in transmit path to only ring access time.
Also store lmac_id in vdev to avoid multi indirection.
Arrange fields in data structure for better alignment in data path access.
Change-Id: I1d32880ed88be486171be46281ec180d2a4906bf
Currently mesh mode uses channel numbering which is derived
from APIs that don't support 6GHz channels numbering due to the
overloading of 6GHz channels with 2.4GHz and 5GHz.
Add support to obtain the correct channel number (and auxiliary
information like band and frequency) through the new APIs that
support 6GHz.
Change-Id: Ib0b39ebae2a22bd6b2b5d17b9058c3c2100e0d59
CRs-Fixed: 2605229
Check the max value for max desc extracted from cfg
before using it for actual allocation of tx descs.
Change-Id: I9bd6c88f136870a42596afbf25328965fce959be
CRs-fixed: 2614329
Memory optimization of unused TX rings by not configuring rings that are
not being used. Configure 2 rings for host in the case of IPA, instead
of configuring 3. If IPA is disabled then configure only 1 set of TX
rings for host.
Change-Id: I251606c728f3020a13e45e8c8386970c8a641f0a
CRs-Fixed: 2530572
Maintain packet counters for each peer based on protocol. Following 3
protocols are supported
* ICMP (IPv4)
* ARP (IPv4)
* EAP
Change-Id: I56dd9bbedd7b6698b7d155a524b242e8cabd76c3
CRs-Fixed: 2604877
A framework is added where the filters for every
mode are stored on a radio instance. Whenever a mode comes
up, it stores the filters in the radio and calls a
common API which iterates through all the enabled
mode filters and loops through them to create a
superset of filters which is sent to HTT.
This framework can be extended for new feature addition
which set filters for the monitor status and monitor
destination rings.
Change-Id: I9b739af2086bbe261b65c57af0a5bd867294f30f
CRs-Fixed: 2585872
Change set 2 of ctrl_ops APIs to replace pdev, vdev and peer
dp handles with pdev_id, vdev_id and peer mac address
along with dp soc handle
Change-Id: I3f180c9c360d564f0b229b447074ad23b7c0a737
Change set 1 of the ctrl_ops APIs to replace pdev, vdev and peer
dp handles with pdev_id, vdev_id and peer mac address
along with dp soc handle
Change-Id: Iedf6dea2215d3d04b2212c71c8ec8c7328c559e8
1. Move all LMAC rings to SOC from pDEV
2. Dynamically obtain lmac->pdev mapping while handling LMAC interrupts
Change-Id: Ib017d49243405b62fc34099c01a2b898b25341d0
the current HAL API is to read the WBM internal error
bit from the wbm release ring descriptor is always taking
HKv1 HW structure. But the wbm_internal_error bit
placement has changed from HKv2, for this reason we have
to use target specific HAL API.
Change-Id: I44789180754ca21ae59650b6d8620321a1f12569
crash scenario:
a. dp_tx_vdev_detach will reset the vdev of TX desc to NULL
by dp_tx_desc_flush.
b. in the meantime, if TX completion is coming and when all TX desc
is recycled, the pool will be freed if pool status is invalid before.
c. invalid TX desc accessing will happen in (a).
add TX desc pool lock protection in dp_tx_desc_flush.
Change-Id: I65c570aa6a3044a478dbe51bbf396cf24612f675
CRs-Fixed: 2595755
Change cmn_ops APIs to replace pdev, vdev and peer
dp handles with pdev_id, vdev_id and peer mac address
along with dp soc handle
Change-Id: I5716a87cad56b1dfe8dd56f193bbb6ff923a6af1
Use dp_info_rl instead of QDF_TRACE when handling tx completion status to
avoid excessive logging when vdev is destroyed in the another thread.
Change-Id: I1044c6d747ba1c7036664fe0265ec4855b7b4c47
CRs-Fixed: 2591486
Increment pdev->num_tx_outstanding when
tx_desc is allocated and decrement tx_desc when tx_desc
is released. During runtime pm suspend, WOW PAUSE
is sent to firmware only if there are no
pending num_tx_outstanding descriptors.
Change-Id: I54aaa4d8a37b8cd47de1701a315bb0735c9739d2
CRs-Fixed: 2567689
Add a check to drop unicast frame being sent to same originating
VAP after hmmc conversion of IGMP control packets
Change-Id: Ic25812a7848af793075a0cb483100ebcf59d85b2
In cases were all the tso tx descriptors are outstanding,
the alloc for any subsequent tso packet will fail.
This failure to get a tso tx descriptor floods the
console with failure logs.
Ratelimit the tso descriptor allocation failure and
increment the alloc failure in stats to get the exact
number of times the allocation failed.
CRs-Fixed: 2572580
Change-Id: I789788b917421be99df5435ad858d715ef0f5c8e
Currently the cdp apis are given pdev/vdev/peer
handle as its arguments, which is directly
accessed in those APIs. This can cause a
race-condition in access of the respective
handles, if it has been deleted in parallel.
Hence as a part of cdp convergence, pass only
the pdev/vdev id or peer mac address, which will be
used to get the respective handles, and hence
avoiding the unwanted access of the handles, if
it has been deleted.
Converged misc_ops
- tx_non_std
- get_opmode
- get_tx_ack_stats
- set_ibss_vdev_heart_beat_timer
- hl_tdls_flag_reset
- set_wisa_mode
- txrx_post_data_stall_event
- update_mac_id
- pkt_log_init
- pkt_log_con_service
- get_num_rx_contexts
- set_wmm_param
- flush_rx_frames
- bad_peer_txctl_set_setting
- bad_peer_txctl_update_threshold
- txrx_data_stall_cb_register
- txrx_data_stall_cb_deregister
- vdev_set_driver_del_ack_enable
- get_intra_bss_fwd_pkts_count
- mark_first_wakeup_packet
- register_pktdump_cb
- unregister_pktdump_cb
- pdev_reset_driver_del_ack
- runtime_suspend
- runtime_resume
CRs-Fixed: 2539811
Change-Id: I3080df033d6411d7078a322224b914bda2fddc0e
Add support to account for TSO jumbo packets on the
Tx path and print the statistics using dumpStats 3.
Change-Id: I6cc446df5c84e3ac436d922935fcd559e0704ec5
CRs-Fixed: 2356244
In the present scenario, in case of Multicast Enhancement when
the multicast packet is received the packet is converted to
unicast packet and send to list of clients in the hyfi table.
During conversion descriptors get allocated from ME pool
for each client and the Tx MSDU descriptor is send to HW
for transmit. On TX completion descriptors are freed and
added back to ME pool.
But if the HW enqueue is failed then the current TX descriptor
is freed and added back to ME pool. But the remaining descriptor
are neither retried nor freed thus resulting in Host Asserted
Crash.
So, adding a fix that if the HW enqueue is failed for ME packet,
free that descriptor and retry HW enqueuing for the remaining
descriptors.
Change-Id: Ibfeb1b07ee8fab4bf066689d0258bb23fb2aa9f8
CRs-Fixed: 2545818
Implement hal_tx_desc_set_mesh_en API
based on the chipset as
the macro to set mesh_en value is
chipset dependent.
Change-Id: I43c85e4ed6fd4f9992de5b71857cdb8becd1dd36
CRs-Fixed: 2522133
Currently after runtime resume all SW2TCL data and reo cmd
srng rings hp and tp value are flushed. In case of IPA
offload case SW2TCL3 righ hp value will be updated by IPA
and not by host. In case of runtime pm enable host is
setting the value to zero as part of runtime resume which
results in incorrect hp value of SW2TCL3. As part of this
change set flush event for rings which are accessed by host
during link down state and after runtime resume flush the
rings for which flush event is set.
Change-Id: I5c9afa708277cf3a6e6d5ef99447bc21f88cfdcf
CRs-Fixed: 2514621
added stats counter to check invalid release reason other than
FW and TQM in tx completion path.
added assert to make sure host is not releasing descriptors with NULL
address.
Change-Id: I3a30bd0f0c3954ed6435489d9b21f16201d1b840
tx_failed is not updated from ppdu completions owing to HW limitation.
Hence update tx_failed from data path
Change-Id: I808223005047af9b474ce423caac27fd9a83677e
This feature enables user to change HW mode dynamically
from DBS to DBS_SBS mode and vice-versa. Currently, HW
mode configuration is only possible through INI setting
requiring a subsequent reboot.
Relevant DP changes are:
1. Add API cdp_txrx_handle_pdev_status_change to pass
pdev 'up' or 'down' status to DP module
2. Add pdev-status check in dp_rx_process_invalid_peer
3. Add pdev-status check in dp_tx_comp_handler to free
buffer and release descriptor
Change-Id: I74b144abb1b0dc41a26a18ad28f872e6457e9653
CRs-fixed: 2490212
HW access to MSDU link Ext descriptor with NULL address,
whie from host MSDU Ext pool and related ring entry history,
not find NULL address recorded. In case the MSDU Ext descriptor
has been overwritten before issue happened, add DMA address
validity checking in MSDU Ext descriptor filled from TSO
segment fragments and also buffer address in ring entry.
Change-Id: I11dc1d0211530a5f01b515473b2458df15a5f4cc
CRs-Fixed: 2498359
1. Remove vlan tag in tx and enqueue to hardware.
2. Add vlan tag in rx after peer-vlan_id lookup.
Change-Id: I932202540ac03cabdd20ffd4849fe759ea8a7abb
Limit the total number of tx descriptors allocated using tx_device_limit
ini configurable parameter.
Change-Id: I00b4aa089b235e45bc6c445c57ce32b977d872c3
Add code to replace usage of void pointers from
HAL layer and instead use appropriate opaque pointers
Change-Id: Id950bd9130a99014305738937aed736cf0144aca
CRs-Fixed: 2487250
