With speculative retire fence, the first commit from HAL depends
on crtc power_on event instead of retire fence signal to unblock
the wait completion. Hence avoid triggering PM suspend/resume if
any of the displays have continuous splash enabled. This will avoid
any state changes in drm_atomic_state and will be inline with
HAL expectation.
Change-Id: I97360e3815651eefdd7e2c1494fa6e882df883b5
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
When VSYNC interrupts are delayed due to irq latencies, there is a
possibility that the timeout handler checking the irq status and the
irq handler clearing the status bit happening at the same time on
different CPU cores. This is reported as an error, though there is
not actual issue. Handle this case, by adding an additional ctl-flush
register check in the vsync timeout handler. As part of the change
add error/eventlogs in commit-done wait failures.
Change-Id: Ie7e30dc4ef1e50651cee9015cd3f2caeacf47e5f
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
On composer kill event, drm lastclose occurs during which suspend
commit gets triggered on primary. If secondary display is stuck in
continuous splash, then we do a early return without triggering
this suspend commit. On composer start, userspace waits for power on
event, but the drm_driver has never entered suspend state, so power
on event is never sent to userspace. This causes HWC deadlock side
effect and the current change triggers null_commit on secondary
display and then issues a suspend commit on both the displays to
avoid this deadlock issue.
Change-Id: I126f43ba3dd2c3bfa83346e8fd4678f35527893d
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change adds one-to-one memory mapping for the hwfence
ipcc register memory needed for hw fence feature.
Change-Id: I0e264183e02d0ed5f2254b409cc5e776d670f0dc
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Starting mdss 9.0, dpu supports triggering
the frame fetch through hw-fencing. This change
adds support for this hw-fence feature.
Change-Id: Icc7d0b69fc2a51103d14612f5ac89b44a47ed826
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Toggle LLCC SCID for each consecutive LLCC write
operations and force read allocate when NSE bit
set.
Change-Id: Ice473cb126b627056b7346f142bc84c120e05f0b
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
This change adds a connector OP, that will be used to update frame
transfer time dynamically at the request from user space.
It also adds parsing for new device tree entries that set the minimum
and maximum trasnfer times on a mode basis. These min and max transfer
times are also published to userspace through the connector mode info
capabilities blob.
Change-Id: I12aedf96a51ff7feb2c5b3b1353d3c4ec8dcb068
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
SID registers and offsets are changed in display
MDSS 9.0.0. Changes are made to program these new registers.
Also, added new revision check for backward
compatibility.
Change-Id: I4e1ea374f38c95a4d1019c2596418bb6bb7c5347
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
Add check to avoid more than 1 CWB active per commit as
hardware doesn't support multiple CWB even if they are
on different OP.
Change-Id: I13416cc2af881de0d8bdd6544a4fdc180fb7a050
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
The sde power event function needs to get actual sde kms irq
number to handle irq update call, but it is not able to know
the irq number before irq installation, so move sde power event
call into kms post init to avoid unbalanced irq issues.
Change-Id: Id262b86f98299fbb9a51c9ccb8e68c7bde7f57ed
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
The splash memory initialized by the bootloader needs
to be released after the first frame update. Add
memblock_free() call to release this memory that was
reserved during the kernel boot.
Change-Id: I463139a3f930dd9284d3ba9516714ead0c77cc02
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
Drop refcount on pm_suspend commit state if atomic
commit is skipped due to failure. It will avoid frame
trigger during pm_resume call.
Change-Id: Ib650ff348ef53122cccad9cb5d200ae295fd2b30
Signed-off-by: Dhaval Patel <quic_pdhaval@quicinc.com>
Use #if IS_ENABLED() instead of #ifdef for configurations as vendor module
guidelines.
Use #if IS_ENABLED(CONFIG_XXX) instead of #ifdef CONFIG_XXX to ensure that
the code inside the #if block continues to compile if the config changes
to a tristate config in the future.
The differences are as follows:
1.#if IS_ENABLED(CONFIG_XXX) evaluates to true when CONFIG_XXX is set to
module (=m) or built-in (=y).
2.#ifdef CONFIG_XXX evaluates to true when CONFIG_XXX is set to
built-in(=y) , but doesn't when CONFIG_XXX is set to module(=m).
Use this only when you're certain you want to do the same thing
when the config is set to module or is disabled.
Change-Id: Ia806b9b01ad8414d0e4de027a382cb68e7fb4a6a
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
The HW support for RGB pipes were removed from MDSS 3.x and cursor pipes
from MDSS 4.x. Remove the support from s/w as well with this change.
Change-Id: Ib5b363234e200ee5c421684cf1904a38a5d90b58
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
pm_runtime_get_sync increases the usage_count refcount immaterial of
success/failure of the call, leading to invalid refcount on failures.
Use pm_runtime_resume_and_get instead, which takes care of reducing the
refcount on failure cases before returning from the function.
Change-Id: Ib96050d5d7ecbd717e58b8a0dde2d03312444e15
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change acquires the vm lock before pre-releasing the
dependent drivers. This avoids any race condition on any
parallel async commands transfers scheduled on connector
drivers. Additionally the main irq line is only disabled
after the pre-release to allow any ongoing transfers
to complete.
Change-Id: Ic0bffc93ebb1b69fbd8d1f096b320a86ad84c857
Signed-off-by: Abhijit Kulkarni <quic_kabhijit@quicinc.com>
If vm has already transitioned from primary to trusted,
triggering a wb/secondary display commit will result in
crash since hw is not owned by the vm. This change adds
necessary changes to fail atomic check in such usecases.
Change-Id: Ic9886d479726c27d1072d12304a87f3bf5deeb76
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
This change adds support in mdp and dsi driver to support
multiple SIS.
Change-Id: I432068cea17e1784d7570a472fbadaa86695df07
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Currently, cwb disable path issues a cleanup flush & waits for the
commit-done. Wait for the tx-done to ensure the transfer is complete.
Change-Id: I509711c157f1d6646646ad96ed140d6bc76d2dba
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
This change sends a notification to user mode after msm_drm
driver releases the mmio and irq resources on trusted vm transition
request. This is required as user mode has no other way to know
when the resources where actually released. User mode driver earlier
relied on retire fence signaling but retire fences are send before
releasing the hw.
Change-Id: Ia218cfcbf398b2de1ad9578fb9baedf348b067df
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
This change moves TVM related code under SDE VM config.
Change-Id: I8357d6a984fd97f18f24eee33464299e8ea66b12
Signed-off-by: Andhavarapu Karthik <quic_kartkart@quicinc.com>
Align the HW catalog to use common naming amongst the "revision"
and "version" structure members.
Change-Id: Ib6c81aee6cb49208b0699db4a75b4eb9dc79e800
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
Move all the individual boolean flags from HW catalog into a
"features" bitmap. These flags are used to specify support of
various target specific features.
Change-Id: I2334b3b873f3737f91bbae4ef576408247710156
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
Remove memblock_free api, since currently is not
part of the ack tree. This prevents modpost compilation
errors for the display driver.
Change-Id: I8f657a123fbecc5d4b029d511b8d08fec2293f0c
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Domain attributes has been deprecated on 5.14 kernel, so replace
msm_smmu_set_attribute with qcom_iommu_enable_s1_translations.
Change-Id: I1bf2d5ee089a418eb73605327e82b2e26bd6bada
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
In the current code, vmlock is always acquired in check
phase even if there is no transition between vm's. This
might result in janks if vmlock is held concurrently by
other processes such as backlight update. This change
ensures that vmlock is held only if there is a valid
transition request between vm's in check phase.
[cohens@codeauarora.org] Resolved trivial merge conflict
and refactored the code to reduce the code complexity.
Change-Id: I022f04c19ba04fdd5494580cc1436747620b9354
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This change allows the commit in preclose to be attempted a
number of times in the event that the return value is -ERESTARTSYS.
This can happen if there is some timing delay which is preventing
the commit to go through completely and an error code is returned.
Change-Id: I26d85d777be182bc153532d7c06f816c934783a4
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Existing LUTDMA hardware runs into issues when an odd number of
LUTDMA absolute address writes are executed before a GDSC power
collapse. Update LUTDMA logic to force absolute write payloads to
always contain an even number of writes.
Change-Id: I476feeab550f4b176d0adccaa5f2d38041e87657
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
Add a utility function to check if HW has been handed over to
another VM.
Change-Id: Ic36ca1e7f15f7608e69d69fc3f4e7ad40be15704
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Early wakeup ioctls from perf HAL driver can access display HW
registers and come as a sideband to atomic commits. Since the
atomic validate checks are not part of this code path it's
possible for HW access to occur during a trusted UI session.
Prevent this whenever the HW is not under this VM's ownership.
Also, move the VM ownership check for the register/deregister
event ioctl to cover both the CRTC and connector events since
new connector events are being added which can access HW.
Change-Id: I39660ae60e7e8f8a405e819c43ec42fbac3f492a
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This change adds support for qsync min refresh rate per
timing mode and populates qsync min refresh rate based
on the current fps when qsync is enabled.
Change-Id: I191d1d72e95dd065c8c0b56a6100104c00c6d8f6
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Demura memory region parsing incorrectly uses the display number
as an extraction index, causing failures in dual panel cases.
Update Demura memory region parsing to always use index 0 during
extraction as each defined region is designed to only declare
a single memory address.
Change-Id: I270f392b636148acd9b891bffcc3cf3d032eab70
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
VA minidumps supports to add any allocated variable or data to
minidumps. Add panic notifier and wrapper function to add
sde data to minidump va. Add event log, register log, register dumps,
debug bus and different sde variables and states info to minidump.
Change-Id: If54da0b7067df17877e4da645d82f1705baa3f6d
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
Delayed work items may touch HW registers. If these work items
run while HW is not owned by this VM it will lead to invalid
access. This happens in video mode as HAL does not disable idle
power-collapse in this mode. It can also happen with ESD status
if lastclose or TUI transition failure occurs.
Although there is a contract with user mode to turn off certain
features, kernel cannot rely on it to always do the right thing.
Prevent potential crashes from certain corner cases by
cancelling all delayed work items when the HW ownership is
transferred.
Change-Id: I08da17f2ce72bf2fddf71924c3e8edd2e2715be8
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
In PM resume with CWB concurrency usecase, crtc pointer in
conn->state is NULL since drm_mode_config_reset operation is
performed on pm_resume. This change relies on conn_mask in
new_crtc_state for primary connector retrieval and also adds
get_num_lm_from_mode callback to DSI for LM count retrieval
from dsi panel topology. Existing get_mode_info api cannot
retrieve the topology info because mode->priv_info is NULL.
This occurs as WB encoder is added in the drm encoder_list
before primary encoder, introduced as part of commit d28ebf05f4
("disp: msm: sde: populate WB display encoder list before dsi").
Change-Id: I55358fd88ab778bd81475cf3628be13335de1cb5
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This change avoids upstream drm issuing drm_atomic_commit in
drm_fb_release which is leading to artifacts on screen or
atomic_check failures due to atomically unstaging each fb
from plane_state and committing remaining planes on hardware.
a) This patch moves the state operations for setting crtc to
connector state to a helper api.
b) This patch clears any dim_layers present in the crtc_state
as part of null commit.
c) This patch removes any framebuffers attached to a drm_file
in msm_preclose whose refcount is not managed by composer kill
inadvertently and issues null flush to hardware in such cases.
d) This patch handles msm_preclose as part of msm_release
operation since legacy feature is not supported
for msm_driver.
Change-Id: Ib2068d74d4b23b73b7c84544858c9f6bb6adfa67
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This change reverts commit ae2dceb0b6 ("disp: msm:
sde: remove all preclose logic"). This change also
modifies the force disable plane logic since
__drm_atomic_helper_disable_plane is not exposed to
drivers.
Change-Id: I89e19dead9ade724798952b1934b45b5663e1a42
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
