Ensure that the driver is handling DSC and FEC
enablement properly. FEC can now be independently
enabled without DSC. FEC configuration is also
now performed after link training in order to
avoid link training failures as per the DP spec.
Consequently, DSC can now be left on during
compliance testing. For DSC use-cases, ensure
that the minimum supported bpp is set to 24, as
required by the DSC spec.
CRs-Fixed: 2517994
Change-Id: I40339585da5b4e51251a3be7119b6959954954d7
Signed-off-by: Fuad Hossain <fhossain@codeaurora.org>
Use one level lower test pattern in case the current
test pattern fails to train link. This helps with few
monitors which sometimes fail with a selected test
pattern. Instead of failing the link, try with a lower
test pattern.
CRs-Fixed: 2507729
Change-Id: I394253398f49b03084dc547dacaededa49a9c527
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
DP specification mandate test pattern #4 for CTS 1.4a. Add
support for the same in link training #2 as per specification.
CRs-Fixed: 2490128
Change-Id: I2f72fec340b56270e7fd1c2940adafe1068bab43
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Adding prefixes for error, debug and info
messages in dp files. To enable debug logs
run "echo 0x100 > /sys/module/drm/parameters/debug"
CRs-Fixed: 2493739
Change-Id: Ibf509e837f527be6bff6b7a1c34b0cde2921b388
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Break the host initialization and de-initialization to
create late initialization and early de-initialization.
Call host init/deinit on physical connect/disconnect only
As attention messages from sink doesn't change the physical
cable configurations, call only late init/early deinit in
this case to avoid unnecessary hardware resources
re-initialization.
CRs-Fixed: 2490128
Change-Id: Ib930d250724ab3ea811a7388c7ad0aeae1164e21
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Update the PLL and PHY power on and clock set sequence as per
the hardware recommendations. Move the post link clock phy enable
part to the catalog so that it can be programmed after enabling
link clock.
Change-Id: I9b3b49e5a9ac93bebcb1cb7da63b715a8d5ed85c
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Add support for new requirements in 1.4a CTS which need
to try link training 1 on different lane counts and link
rates.
CRs-Fixed: 2458753
Change-Id: I2039822f420a73232df7293afcddd7bee263c7b4
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Update the link training process along with the AUX
communications during link training as per hardware
recommendations.
Update the pre-emphasis and swing values for active
lanes only instead of all lanes.
During link training, update pre-emphasis and swing
values in hardware first and then update sink.
CRs-Fixed: 2458753
Change-Id: Ie05c9d6508b0c564b194032ae4ebb1bc5550e7b8
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Add support for lane count reduction as per the new requirements
for DP 1.4a during link training 2.
CRs-Fixed: 2458753
Change-Id: I58c9b6101338e8a1d1b4e3dec80f8fdf2a25ae5b
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Update the DP controller and PHY programming according to
the new hardware recommendations.
CRs-Fixed: 2458753
Change-Id: I1bce5915ba6ebbb250cc5c4aac907b0b287eece7
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
This change brings msm display driver including sde,
dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel
project. It is first source code snapshot from base kernel project.
Change-Id: Iec864c064ce5ea04e170f24414c728684002f284
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
