Starting with HW-Fencing, the frames hw kickoff
can take longer to trigger, given that HW will wait for the
input fences signal. Therefore, this change increments
the time-outs to wait up to ~10 secs, which corresponds
to the current input dma-fences timeout. This ~10secs
wait is given in intervals, where the dma-fence is also
checked, so in case that the client producer of the fence
signals the dma-fence, but misses the hw-fence signaling,
Display driver can handle this case and do a sw-override
to start the fetching of the incoming frame without waiting
for the input hw-fence ipc signal.
Change-Id: I6fcacbbaa79ca9847da616bd52efdda4bb8fccae
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change adds debug changes to dump the input fences during a
commit done timeout, when input hw-fences are enabled.
Change-Id: Ia778d3d73ab8ee795613587da70ef9bebb7c73ca
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
The cwb_enc_mask is set by the wb phys encoder during the validate
phase and this is in-turn used during the commit phase. During
seamless transition cases like poms with cwb, the encoders are
disabled and then enabled back after the validate phase. The cwb
flags are reset during this time leading to issues. Cache the flag
and reapply it during the modeset to avoid this case.
Change-Id: I5df1be18a5e30bb1107dc0f2e87d771a735f1ab6
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Starting mdss 9.0, dpu supports triggering
the frame fetch through hw-fencing. This change
adds support for this hw-fence feature.
Change-Id: Icc7d0b69fc2a51103d14612f5ac89b44a47ed826
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change collects the OPR, MISR values. If the values are
different than the previous then notify to client with custom event.
Change-Id: I2546439be1f665d90e6505d65283d28096bf7cdd
Signed-off-by: Akshay Ashtunkar <quic_akshayaa@quicinc.com>
Toggle LLCC SCID for each consecutive LLCC write
operations and force read allocate when NSE bit
set.
Change-Id: Ice473cb126b627056b7346f142bc84c120e05f0b
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Add line insertion support for sspp, this is used to support
display with external splitter. Line insertion logic checks
the difference between screen logical height and physical
height. If any difference is observed adds dummy and active
lines on screen.
Change-Id: Ieec322273df000a53fb39e05174c2d67c3c2da81
Signed-off-by: Rajesh kv <quic_kvrajesh@quicinc.com>
* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
Add support to parse and configure QoS values for offline writeback.
Expose a writeback connector property to allow user-mode to set
the usage type of the writeback block - WFD, CWB, offline-WB.
Change-Id: I864f79c4896ec757ac2d8b0f57a6a5775d164f21
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
As per HW recommendation, FAL10_VETO_OVERRIDE register can
be programmed to disable FAL10 in alternate to disabling
uidle at the sspp level as disabling UIDLE controller will
only disable DPU traffic shaping and will not stop the
system from entering FAL10 state. This change programs
FAL10_VETO_OVERRIDE register during uidle disable and also
sets CTL_x_UIDLE_ACTIVE register to always one to avoid
race condition between different CTL paths.
Change-Id: I9c55f5da2037cb8c448cc978eac0a04608a93650
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
This change reinitializes the sde_crtc->mixers when CTL
datapath switch occurs during mode set and RM allocation
of CTL hw block is changed. This initialization is required
for CTL_LAYER programming to trigger on the new CTL allocated
from RM.
Issue case:
1. Primary Display is using CTL_0 and it is reserved.
2. Secondary Display is using CTL_1. On suspend, RM adds
CTL_1 into the free list.
3. External Display is powered on, RM allocates CTL_1 hw blk.
4. Secondary Display is powered on, RM allocated CTL_2 hw blk.
5. External Display is suspended/unplugged, RM adds CTL_1 into
the free list.
6. When any mode_set(say fps switch) occurs on secondary, RM
allocates new resources and CTL_1 is allocated.
sde_crtc->num_mixers is non zero, so all the layer programming
happens on CTL_2, but CTL_1_FLUSH bits are programmed causing
hw timeout issue.
Change-Id: I5f1f52b7673740c48b249ab4d36e80b7a1d3db96
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Add downscale blur block validations in atomic_check phase of writeback
encoder. Downscale blur along with partial update is not supported.
NV12 output in WB is not supported with downscale blur as CDM block
usage is mutually exclusive with dsnc_blur. If destination scaler is
enabled, the ds src or dst should match with dnsc_blur src based on
the ds tap point chosen.
Change-Id: I1d643dc26738c0e77d8e9181b4c834693153209c
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
When downscale blur feature is enabled, calculate the mixex and crtc
width and height using the dnsc_blur's src width & height. Update the
sde_crtc_get_mixer width/height functions to return the correct size
based on the features enabled.
Change-Id: I52dd88cc52e1ca5cb37e381e92e0e3032e7b090f
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add a custom cache_enable property in writeback connector to allow
user-mode to control the cache setting on a frame basis. Configure
the hw and activate/deactivate the llcc based on the property. The
custom property is added based on the availability of the system
cache for writeback.
Change-Id: I812b31955eb36c75c33ac279b56502a13f7cdcbf
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
The interface resolution can be different from crtc/layer-mixer WxH
when certain features like destination scaler are enabled. Use the
sde_crtc_get_width/sde_crtc_get_mixer_width functions throughout
to get the correct crtc/lm size based on different features enabled.
This will help in validating/configuring lm & plane correctly.
Change-Id: I45de5844bf7465a3389cf723479c5449a835fb0a
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
uidle_db_updates are generated when CTL_x_UIDLE_ACTIVE is set to 1.
It needs to enabled in both uidle enable and disable cases.
CTL_x_UIDLE_ACTIVE is set to 0 only in cases where uidle configuration
is not updated.
Change-Id: If7655e4eae351bac248f0906c473cdfaf93f2b8a
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This change deprecates idle notify work for video mode
since idle timer will be maintained by userspace.
As part of idle notify work, syscache state is changed from
CACHE_STATE_NORMAL to CACHE_STATE_PRE_CACHE along with
notifying to the userspace. This change removes
CACHE_STATE_PRE_CACHE in the state machine and state is
updated from CACHE_STATE_NORMAL to CACHE_STATE_FRAME_WRITE
whenever the cache property is set.
Change-Id: If3b2c34be954cb625aca76da81fd854c077a8250
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
This change sends a notification to user mode after msm_drm
driver releases the mmio and irq resources on trusted vm transition
request. This is required as user mode has no other way to know
when the resources where actually released. User mode driver earlier
relied on retire fence signaling but retire fences are send before
releasing the hw.
Change-Id: Ia218cfcbf398b2de1ad9578fb9baedf348b067df
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Current timeout values in sde driver for vblank, kickoff and
frame complete timeouts are fixed and can be much lower than
a vsync incase of low refresh rate display. Compute timeouts
based on refresh rate for low refresh rate displays.
Change-Id: I9dda41feb15446de7451824e185321de421ad575
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
When all instances of driver fd's are closed by user-space client, drm driver
will be closed. When last close of driver is called, custom reset properties
api will be called where driver should cache the properties that it wants to
clear. Current behavior of color processing driver is to clear hardware
configuration instead of caching which can cause crashes if clocks are off.
Change updates the driver to cache the pending disable and update hardware
during display commit.
Change-Id: I9703f860ed0ae3c859d6fc3995b58be13203f259
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Delayed work items may touch HW registers. If these work items
run while HW is not owned by this VM it will lead to invalid
access. This happens in video mode as HAL does not disable idle
power-collapse in this mode. It can also happen with ESD status
if lastclose or TUI transition failure occurs.
Although there is a contract with user mode to turn off certain
features, kernel cannot rely on it to always do the right thing.
Prevent potential crashes from certain corner cases by
cancelling all delayed work items when the HW ownership is
transferred.
Change-Id: I08da17f2ce72bf2fddf71924c3e8edd2e2715be8
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Add changes to modify the phys_enc->in_clone_mode variable
post wb_reset_state since this is a shared variable used
during atomic_check and atomic_commit. In current issue case,
wb_atomic_check has set in_clone_mode to true in commit N,
and in commit N-1 CWB is being disabled and re-sets the
in_clone_mode variable to false causing pp_done timeouts in
primary in commit N.
Change-Id: I8159bbdb5622a351d76bdc4dba75d48df20f4365
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
In PM resume with CWB concurrency usecase, crtc pointer in
conn->state is NULL since drm_mode_config_reset operation is
performed on pm_resume. This change relies on conn_mask in
new_crtc_state for primary connector retrieval and also adds
get_num_lm_from_mode callback to DSI for LM count retrieval
from dsi panel topology. Existing get_mode_info api cannot
retrieve the topology info because mode->priv_info is NULL.
This occurs as WB encoder is added in the drm encoder_list
before primary encoder, introduced as part of commit d28ebf05f4
("disp: msm: sde: populate WB display encoder list before dsi").
Change-Id: I55358fd88ab778bd81475cf3628be13335de1cb5
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
During idle power collapse, dim layer dirty flags are
stored in sde_crtc_state which might be invalid if state
swap occurs. This change adds revalidate mask in sde_crtc
structure to revalidate after coming out of idle power
collapse.
Change-Id: Ie2f34a794896a3f8e729ef7d1f3ae35340123257
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This change avoids upstream drm issuing drm_atomic_commit in
drm_fb_release which is leading to artifacts on screen or
atomic_check failures due to atomically unstaging each fb
from plane_state and committing remaining planes on hardware.
a) This patch moves the state operations for setting crtc to
connector state to a helper api.
b) This patch clears any dim_layers present in the crtc_state
as part of null commit.
c) This patch removes any framebuffers attached to a drm_file
in msm_preclose whose refcount is not managed by composer kill
inadvertently and issues null flush to hardware in such cases.
d) This patch handles msm_preclose as part of msm_release
operation since legacy feature is not supported
for msm_driver.
Change-Id: Ib2068d74d4b23b73b7c84544858c9f6bb6adfa67
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
In dual display usecases, during pm suspend/resume,
commit is scheduled only on primary crtc thread. If idle
timeout value is very short such as in LP2 mode, it might
result in race condition due to idle pc off work getting
scheduled on its crtc thread. This change adds kickoff in
progress flag to handle such cases as crtc frame pending
count is only updated after rc kickoff.
Change-Id: Iebb331d914b23cc5eeadfeb2a488891e88b3202a
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
During one of the DP timeout usecases, flush doesn't take
effect due to vid vblank wait failure. As a result, smmu
faults are observed because of fetching the previously
staged planes. This change adds ctl reset in the same
DP atomic commit context to recover and avoid
smmu faults.
Change-Id: I2f9aceca56e27f140607317f7596d6fe0d908af8
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
When LTM is switching on/off, merge_mode bit value gets toggled between
0x1 (dual pipe merge configuration) and 0x0 (single pipe configuration).
It is illegal to reconfigure LTM to/from dual-pipe merge mode before
both LTM instances have completed their current workloads. This change
adds support to disable merge_mode one frame after histogram is disabled
to make sure both hardware instances are completely idle and avoid
corrupted histogram data collection.
Change-Id: I9a6b5cbfb69e8af7936749e57fe7c8f7c2703b95
Signed-off-by: Ping Li <pingli@codeaurora.org>
Add support to send a data packet of info, written to
predefined buffers, providing information about each submitted frame.
Add required UAPI definitions for frame data buffers and event
notification.
Add support to read ubwc statistics from hw, based on defined rois.
Change-Id: I51f279de98ae4e2a02b0df6943d334764011d5db
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Move the hist irq handling out of callback function, i.e., the hw
interrupt irq_lock context, to avoid dead lock between crtc spin_lock
and irq_lock. This change also extends crtc spin_lock coverage in
_sde_cp_crtc_enable_hist_irq to prevent null pointer dereference on
event node, which can be deleted during crtc event de-registration.
Change-Id: Iadaed54ab93c4c4abe065a8762d2addccb0c65c6
Signed-off-by: Ping Li <pingli@codeaurora.org>
Due to lock sequence inconsistency between sde_crtc->spin_lock and
sde_kms->hw_intr->irq_lock can cause deadlock, to avoid this possible
deadlock this change uses different spin lock for frame events.
Change-Id: I51b1184dfa1069c87653099b95b992b277721daf
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Calculate line_time once during modeset and allow
each plane to use it instead of calculating for each frame.
It also simplifies the line_time calculation for
command mode display.
Change-Id: I94ce29eec94bfdbee9016fbf93378661ebf79c03
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
HFC feature of demura needs a skip blend plane to be set. If skip blend
plane is not set and HFC feature is requested to be enabled, driver
should skip turning on HFC demura feature. Change adds checks to ensure
that HFC is always enabled with skip blend plane staged.
Change-Id: I923359c7cb143867660b4c1e667f56ed42fa51c9
Encoder is disabling planes and unstaging layers from layer mixer. Some
of the crtc features are dependent on the plane being staged. Change
adds api that encoder can call on crtc to stop the features that are
dependent on source pipes.
Change-Id: I4d875155ceb8f66acfe6ce0096141ca7253bb140
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Declare the continuous splash pipeline setup to userspace by filling
in the DRM states for all plane, crtc, encoder, and connector objects
in use. This information will be treated as an 'informative' state,
and will be cleared at the start of the first commit to maintain
the DRM methodology of DRM clients being the only controller of
the pipeline. This ensures any configuration provided by userspace
is accepted and applied, even if it may already align with the setup
done by continuous splash.
This DRM state configuration is done via manual modification of the
DRM object states. Modification via the exposed DRM UAPI functions
is not possible due to no drm_atomic_state object linking the DRM
pipeline objects together.
Change-Id: I67650e05aafbb4e799cf60939f0595bc3786fc6e
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
As the number of cp features has continued to grow, the file
sde_color_processing has become increasingly harder to parse.
Update function and parameter names to better identify internal
functions and increase readability.
Change-Id: Ib82d6c9a45b36b932ab3a2d573b7cbe13a6c10bc
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
Recent investigation shows that color processing properties are
incorrectly being cached in validate. This can result in unwanted
color processing properties being applied if a previous commit
failed or was validate only.
Add color processing properties to sde crtc state instead of marking
them dirty in color processing driver. When atomic commit is called
properties from state will be marked as dirty and applied.
Change-Id: If231a1f028e4cbd0b50eb0a947f4d58f94390a0c
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
This reverts commit 6886d03e4a.
It tries to memset the pstate from UI thread (crtc atomic check)
and crtc commit thread.
Change-Id: Ic9d3e5555d7085832df76025e53488d2b3365739
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
DPU has added support for noise injection into the layer stack. Change
adds support for noise layer programming and exposes the hardware block
to the user space modules.
Change-Id: Id176eea54fcdcd5d399457b14133a1ccde07299f
Add new capture/tap point as CRTC property for
D-CWB feature. Update the hardware blocks and
corresponding APIs to configure D-CWB data path.
Add new hardware pingpong blocks that
are dedicated for CWB.
Change-Id: I22576df1768b50f9f47d8527f62913b01ff4d9a7
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
