提交图

8 次代码提交

作者 SHA1 备注 提交日期
Sandeep Gangadharaiah
e4e277ad36 disp: msm: dp: Convert clock operations to byte2 ops
Convert clock operation to byte2 ops to meet DISPCC requirement.
Clock unit is changed from KHZ to HZ. Added link clock parent as
freq table is no longer supported in byte2 ops.

Change-Id: Icf5a595708040e8afefecebe7f371bb832d6673e
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-10-27 15:39:14 -07:00
Sandeep Gangadharaiah
b5383dbae3 disp: msm: dp: add pll params table for 4nm PHY pll settings
Because of changes to ref clock frequency, few of the pll
reg values are different for kalama compared to palima.
This change differentiates between these two 4nm versions,
based on pll revision and also introduces a pll reg table
to differentiate the values.

Change-Id: I016330ded10ab334012daa8cc288a8cd5c039f58
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-03-10 14:13:40 -08:00
Vara Reddy
7230476c9c disp: msm: dp: calculate mvid and nvid dividers with in DP driver
Change removes the dependency of reading MVID and NVID settings
from dispcc registers and calculates the values locally in displayport
driver.

Change-Id: I9ad66aea44a3cbc0f739060c49e23d389022a48a
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
2022-03-02 15:34:40 -08:00
Soutrik Mukhopadhyay
bbc87c5dde disp: msm: dp: add support for 4nm DP PLL
Changes include support for 4nm DP PHY and DP PLL.
Added dp_pll_4nm.c file with register programming
sequences for DP PHY and PLL.

Change-Id: I104cf69964904c9a47a17e75a84df011d7994c9f
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
2021-11-27 09:39:07 +05:30
Tatenda Chipeperekwa
c6257272d4 disp: msm: fix compilation errors for dlkm compilation
Fix dlkm compilation errors that are due to the use of -Werror
flags used by the build system.

Change-Id: I5e1e9bc63c1361d73e4930aab123212717872ecb
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
2021-03-22 15:25:36 -07:00
Sudarsan Ramesh
e66a2089f4 disp: msm: dp: update pll driver to fix clock names per target
With the change in the clock names for newer targets, this fix
updates the driver to support different clock names per target.

Change-Id: I58c35fce34356f8c79adb0ac8a907e2fb60813ae
Signed-off-by: Sudarsan Ramesh <sudarame@codeaurora.org>
2021-03-01 11:09:15 -05:00
Yuan Zhao
600416fa77 disp: msm: dp: replace dp clock trees with single nodes
The current pll driver models the entire DP clock
hierarchy using the clock framework. This creates
unnecessary dependency between the dp driver and
the clock driver and also limits the flexibility
to dp driver when configuring the DP clocks.

This change models these clocks as single nodes
and provide full control to the dp driver and
also minimizes the dependency on the clock driver.

Change-Id: Id5221441ea33b576e7c543396a12cbeb7b44d319
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
2021-01-13 01:18:08 -08:00
Tatenda Chipeperekwa
37412f5add disp: msm: dp: add support for PLL programming
Add support for PLL programming in the DisplayPort driver.

Change-Id: I4f08a621dcae5d1f54d67bb5c34409249012cc7b
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
2020-03-13 20:26:39 -07:00